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a10c01a6c6
Swift cores implement store barriers that are stronger than the ARM specification but weaker than general barriers. They are, in fact, just about enough to provide the ordering needed for atomic operations with release semantics. This patch makes use of that quirk. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185527 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1.2 KiB
LLVM
46 lines
1.2 KiB
LLVM
; RUN: llc -mtriple=armv7-apple-ios6.0 -mcpu=swift < %s | FileCheck %s
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; RUN: llc -mtriple=armv7-apple-ios6.0 < %s | FileCheck %s --check-prefix=CHECK-STRICT-ATOMIC
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; Release operations only need the store barrier provided by a "dmb ishst",
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define void @test_store_release(i32* %p, i32 %v) {
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; CHECK: test_store_release:
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; CHECK: dmb ishst
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; CHECK: str
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; CHECK-STRICT-ATOMIC: dmb {{ish$}}
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store atomic i32 %v, i32* %p release, align 4
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ret void
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}
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; However, if sequential consistency is needed *something* must ensure a release
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; followed by an acquire does not get reordered. In that case a "dmb ishst" is
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; not adequate.
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define i32 @test_seq_cst(i32* %p, i32 %v) {
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; CHECK: test_seq_cst:
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; CHECK: dmb ishst
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; CHECK: str
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; CHECK: dmb {{ish$}}
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; CHECK: ldr
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; CHECK: dmb {{ish$}}
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; CHECK-STRICT-ATOMIC: dmb {{ish$}}
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; CHECK-STRICT-ATOMIC: dmb {{ish$}}
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store atomic i32 %v, i32* %p seq_cst, align 4
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%val = load atomic i32* %p seq_cst, align 4
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ret i32 %val
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}
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; Also, pure acquire operations should definitely not have an ishst barrier.
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define i32 @test_acq(i32* %addr) {
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; CHECK: test_acq:
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; CHECK: ldr
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; CHECK: dmb {{ish$}}
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; CHECK-STRICT-ATOMIC: dmb {{ish$}}
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%val = load atomic i32* %addr acquire, align 4
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ret i32 %val
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}
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