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Abort if we see a PCRelativeDisp MachineOperand, to be safe. This matches the X86 backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14202 91177308-0d34-0410-b5e6-96231b3b80d8
773 lines
29 KiB
C++
773 lines
29 KiB
C++
//===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a simple peephole instruction selector for the V8 target
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8.h"
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#include "SparcV8InstrInfo.h"
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#include "llvm/Instructions.h"
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#include "llvm/IntrinsicLowering.h"
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#include "llvm/Pass.h"
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#include "llvm/Constants.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/GetElementPtrTypeIterator.h"
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#include "llvm/Support/InstVisitor.h"
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#include "llvm/Support/CFG.h"
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using namespace llvm;
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namespace {
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struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
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TargetMachine &TM;
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MachineFunction *F; // The function we are compiling into
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MachineBasicBlock *BB; // The current MBB we are compiling
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std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
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// MBBMap - Mapping between LLVM BB -> Machine BB
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std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
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V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
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/// runOnFunction - Top level implementation of instruction selection for
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/// the entire function.
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///
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bool runOnFunction(Function &Fn);
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virtual const char *getPassName() const {
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return "SparcV8 Simple Instruction Selection";
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}
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/// emitGEPOperation - Common code shared between visitGetElementPtrInst and
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/// constant expression GEP support.
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///
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void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
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Value *Src, User::op_iterator IdxBegin,
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User::op_iterator IdxEnd, unsigned TargetReg);
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/// visitBasicBlock - This method is called when we are visiting a new basic
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/// block. This simply creates a new MachineBasicBlock to emit code into
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/// and adds it to the current MachineFunction. Subsequent visit* for
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/// instructions will be invoked for all instructions in the basic block.
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///
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void visitBasicBlock(BasicBlock &LLVM_BB) {
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BB = MBBMap[&LLVM_BB];
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}
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void visitBinaryOperator(Instruction &I);
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void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
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void visitSetCondInst(Instruction &I);
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void visitCallInst(CallInst &I);
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void visitReturnInst(ReturnInst &I);
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void visitBranchInst(BranchInst &I);
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void visitCastInst(CastInst &I);
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void visitLoadInst(LoadInst &I);
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void visitStoreInst(StoreInst &I);
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void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
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void visitGetElementPtrInst(GetElementPtrInst &I);
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void visitInstruction(Instruction &I) {
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std::cerr << "Unhandled instruction: " << I;
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abort();
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}
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/// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
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/// function, lowering any calls to unknown intrinsic functions into the
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/// equivalent LLVM code.
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void LowerUnknownIntrinsicFunctionCalls(Function &F);
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void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
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void LoadArgumentsToVirtualRegs(Function *F);
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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void copyConstantToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Constant *C, unsigned R);
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/// makeAnotherReg - This method returns the next register number we haven't
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/// yet used.
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///
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/// Long values are handled somewhat specially. They are always allocated
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/// as pairs of 32 bit integer values. The register number returned is the
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/// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
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/// of the long value.
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///
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unsigned makeAnotherReg(const Type *Ty) {
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assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
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"Current target doesn't have SparcV8 reg info??");
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const SparcV8RegisterInfo *MRI =
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static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
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if (Ty == Type::LongTy || Ty == Type::ULongTy) {
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const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
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// Create the lower part
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F->getSSARegMap()->createVirtualRegister(RC);
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// Create the upper part.
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return F->getSSARegMap()->createVirtualRegister(RC)-1;
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}
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// Add the mapping of regnumber => reg class to MachineFunction
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const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
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return F->getSSARegMap()->createVirtualRegister(RC);
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}
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unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
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unsigned getReg(Value *V) {
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// Just append to the end of the current bb.
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MachineBasicBlock::iterator It = BB->end();
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return getReg(V, BB, It);
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}
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unsigned getReg(Value *V, MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IPt) {
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unsigned &Reg = RegMap[V];
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if (Reg == 0) {
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Reg = makeAnotherReg(V->getType());
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RegMap[V] = Reg;
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}
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// If this operand is a constant, emit the code to copy the constant into
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// the register here...
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//
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if (Constant *C = dyn_cast<Constant>(V)) {
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copyConstantToRegister(MBB, IPt, C, Reg);
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RegMap.erase(V); // Assign a new name to this constant if ref'd again
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} else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
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// Move the address of the global into the register
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unsigned TmpReg = makeAnotherReg(V->getType());
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BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
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BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
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.addGlobalAddress (GV);
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RegMap.erase(V); // Assign a new name to this address if ref'd again
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}
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return Reg;
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}
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};
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}
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FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
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return new V8ISel(TM);
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}
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enum TypeClass {
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cByte, cShort, cInt, cLong, cFloat, cDouble
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};
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static TypeClass getClass (const Type *T) {
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switch (T->getTypeID()) {
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case Type::UByteTyID: case Type::SByteTyID: return cByte;
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case Type::UShortTyID: case Type::ShortTyID: return cShort;
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case Type::PointerTyID:
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case Type::UIntTyID: case Type::IntTyID: return cInt;
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case Type::ULongTyID: case Type::LongTyID: return cLong;
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case Type::FloatTyID: return cFloat;
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case Type::DoubleTyID: return cDouble;
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default:
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assert (0 && "Type of unknown class passed to getClass?");
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return cByte;
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}
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}
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static TypeClass getClassB(const Type *T) {
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if (T == Type::BoolTy) return cByte;
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return getClass(T);
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}
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Constant *C, unsigned R) {
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if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
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switch (CE->getOpcode()) {
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case Instruction::GetElementPtr:
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emitGEPOperation(MBB, IP, CE->getOperand(0),
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CE->op_begin()+1, CE->op_end(), R);
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return;
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default:
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std::cerr << "Copying this constant expr not yet handled: " << *CE;
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abort();
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}
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}
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if (C->getType()->isIntegral ()) {
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uint64_t Val;
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unsigned Class = getClassB (C->getType ());
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if (Class == cLong) {
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unsigned TmpReg = makeAnotherReg (Type::IntTy);
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unsigned TmpReg2 = makeAnotherReg (Type::IntTy);
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// Copy the value into the register pair.
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// R = top(more-significant) half, R+1 = bottom(less-significant) half
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uint64_t Val = cast<ConstantInt>(C)->getRawValue();
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unsigned topHalf = Val & 0xffffffffU;
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unsigned bottomHalf = Val >> 32;
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unsigned HH = topHalf >> 10;
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unsigned HM = topHalf & 0x03ff;
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unsigned LM = bottomHalf >> 10;
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unsigned LO = bottomHalf & 0x03ff;
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(HH);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (HM);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg2).addImm(LM);
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BuildMI (*MBB, IP, V8::ORri, 2, R+1).addReg (TmpReg2)
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.addImm (LO);
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return;
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}
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assert(Class <= cInt && "Type not handled yet!");
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if (C->getType() == Type::BoolTy) {
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Val = (C == ConstantBool::True);
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} else {
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ConstantInt *CI = dyn_cast<ConstantInt> (C);
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Val = CI->getRawValue ();
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}
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switch (Class) {
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case cByte:
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm((uint8_t)Val);
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return;
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case cShort: {
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unsigned TmpReg = makeAnotherReg (C->getType ());
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
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.addImm (((uint16_t) Val) >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (((uint16_t) Val) & 0x03ff);
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return;
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}
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case cInt: {
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unsigned TmpReg = makeAnotherReg (C->getType ());
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(((uint32_t)Val) >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (((uint32_t) Val) & 0x03ff);
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return;
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}
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default:
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std::cerr << "Offending constant: " << *C << "\n";
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assert (0 && "Can't copy this kind of constant into register yet");
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return;
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}
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} else if (isa<ConstantPointerNull>(C)) {
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// Copy zero (null pointer) to the register.
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm (0);
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} else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
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// Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
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// that SETHI %reg,global == SETHI %reg,%hi(global) and
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// OR %reg,global,%reg == OR %reg,%lo(global),%reg.
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unsigned TmpReg = makeAnotherReg (C->getType ());
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress (CPR->getValue());
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addGlobalAddress (CPR->getValue ());
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} else {
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std::cerr << "Offending constant: " << *C << "\n";
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assert (0 && "Can't copy this kind of constant into register yet");
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}
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}
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void V8ISel::LoadArgumentsToVirtualRegs (Function *F) {
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unsigned ArgOffset = 0;
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static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
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V8::I3, V8::I4, V8::I5 };
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assert (F->asize () < 7
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&& "Can't handle loading excess call args off the stack yet");
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for (Function::aiterator I = F->abegin(), E = F->aend(); I != E; ++I) {
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unsigned Reg = getReg(*I);
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switch (getClassB(I->getType())) {
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case cByte:
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case cShort:
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case cInt:
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BuildMI(BB, V8::ORrr, 2, Reg).addReg (V8::G0)
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.addReg (IncomingArgRegs[ArgOffset]);
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break;
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default:
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assert (0 && "Only <=32-bit, integral arguments currently handled");
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return;
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}
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++ArgOffset;
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}
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}
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bool V8ISel::runOnFunction(Function &Fn) {
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// First pass over the function, lower any unknown intrinsic functions
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// with the IntrinsicLowering class.
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LowerUnknownIntrinsicFunctionCalls(Fn);
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F = &MachineFunction::construct(&Fn, TM);
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// Create all of the machine basic blocks for the function...
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for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
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F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
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BB = &F->front();
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// Set up a frame object for the return address. This is used by the
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// llvm.returnaddress & llvm.frameaddress intrinisics.
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//ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
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// Copy incoming arguments off of the stack and out of fixed registers.
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LoadArgumentsToVirtualRegs(&Fn);
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// Instruction select everything except PHI nodes
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visit(Fn);
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// Select the PHI nodes
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//SelectPHINodes();
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RegMap.clear();
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MBBMap.clear();
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F = 0;
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// We always build a machine code representation for the function
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return true;
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}
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void V8ISel::visitCastInst(CastInst &I) {
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unsigned SrcReg = getReg (I.getOperand (0));
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unsigned DestReg = getReg (I);
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const Type *oldTy = I.getOperand (0)->getType ();
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const Type *newTy = I.getType ();
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unsigned oldTyClass = getClassB (oldTy);
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unsigned newTyClass = getClassB (newTy);
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if (oldTyClass < cLong && newTyClass < cLong) {
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if (oldTyClass >= newTyClass) {
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// Emit a reg->reg copy to do a equal-size or narrowing cast,
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// and do sign/zero extension (necessary if we change signedness).
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unsigned TmpReg1 = makeAnotherReg (newTy);
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unsigned TmpReg2 = makeAnotherReg (newTy);
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BuildMI (BB, V8::ORrr, 2, TmpReg1).addReg (V8::G0).addReg (SrcReg);
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unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
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BuildMI (BB, V8::SLLri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
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if (newTy->isSigned ()) { // sign-extend with SRA
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BuildMI(BB, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg2);
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} else { // zero-extend with SRL
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BuildMI(BB, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg2);
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}
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} else {
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unsigned TmpReg1 = makeAnotherReg (oldTy);
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unsigned TmpReg2 = makeAnotherReg (newTy);
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unsigned TmpReg3 = makeAnotherReg (newTy);
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// Widening integer cast. Make sure it's fully sign/zero-extended
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// wrt the input type, then make sure it's fully sign/zero-extended wrt
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// the output type. Kind of stupid, but simple...
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unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (oldTy));
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BuildMI (BB, V8::SLLri, 2, TmpReg1).addZImm (shiftWidth).addReg(SrcReg);
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if (oldTy->isSigned ()) { // sign-extend with SRA
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BuildMI(BB, V8::SRAri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
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} else { // zero-extend with SRL
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BuildMI(BB, V8::SRLri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
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}
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shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
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BuildMI (BB, V8::SLLri, 2, TmpReg3).addZImm (shiftWidth).addReg(TmpReg2);
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if (newTy->isSigned ()) { // sign-extend with SRA
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BuildMI(BB, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg3);
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} else { // zero-extend with SRL
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BuildMI(BB, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg3);
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}
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}
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} else {
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std::cerr << "Casts w/ long, fp, double still unsupported: " << I;
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abort ();
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}
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}
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void V8ISel::visitLoadInst(LoadInst &I) {
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unsigned DestReg = getReg (I);
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unsigned PtrReg = getReg (I.getOperand (0));
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switch (getClassB (I.getType ())) {
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case cByte:
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if (I.getType ()->isSigned ())
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BuildMI (BB, V8::LDSBmr, 1, DestReg).addReg (PtrReg).addSImm(0);
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else
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BuildMI (BB, V8::LDUBmr, 1, DestReg).addReg (PtrReg).addSImm(0);
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return;
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case cShort:
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if (I.getType ()->isSigned ())
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BuildMI (BB, V8::LDSHmr, 1, DestReg).addReg (PtrReg).addSImm(0);
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else
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BuildMI (BB, V8::LDUHmr, 1, DestReg).addReg (PtrReg).addSImm(0);
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return;
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case cInt:
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BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
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return;
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case cLong:
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BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
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return;
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default:
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std::cerr << "Load instruction not handled: " << I;
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abort ();
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return;
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}
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}
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void V8ISel::visitStoreInst(StoreInst &I) {
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Value *SrcVal = I.getOperand (0);
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unsigned SrcReg = getReg (SrcVal);
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unsigned PtrReg = getReg (I.getOperand (1));
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switch (getClassB (SrcVal->getType ())) {
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case cByte:
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BuildMI (BB, V8::STBrm, 1, SrcReg).addReg (PtrReg).addSImm(0);
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return;
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case cShort:
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BuildMI (BB, V8::STHrm, 1, SrcReg).addReg (PtrReg).addSImm(0);
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return;
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case cInt:
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BuildMI (BB, V8::STrm, 1, SrcReg).addReg (PtrReg).addSImm(0);
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return;
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case cLong:
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BuildMI (BB, V8::STDrm, 1, SrcReg).addReg (PtrReg).addSImm(0);
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return;
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default:
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std::cerr << "Store instruction not handled: " << I;
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abort ();
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return;
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}
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}
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void V8ISel::visitCallInst(CallInst &I) {
|
|
assert (I.getNumOperands () < 8
|
|
&& "Can't handle pushing excess call args on the stack yet");
|
|
static const unsigned OutgoingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3,
|
|
V8::O4, V8::O5 };
|
|
for (unsigned i = 1; i < 7; ++i)
|
|
if (i < I.getNumOperands ()) {
|
|
unsigned ArgReg = getReg (I.getOperand (i));
|
|
// Schlep it over into the incoming arg register
|
|
BuildMI (BB, V8::ORrr, 2, OutgoingArgRegs[i - 1]).addReg (V8::G0)
|
|
.addReg (ArgReg);
|
|
}
|
|
|
|
BuildMI (BB, V8::CALL, 1).addGlobalAddress(I.getCalledFunction (), true);
|
|
if (I.getType () == Type::VoidTy)
|
|
return;
|
|
unsigned DestReg = getReg (I);
|
|
// Deal w/ return value
|
|
switch (getClass (I.getType ())) {
|
|
case cByte:
|
|
case cShort:
|
|
case cInt:
|
|
// Schlep it over into the destination register
|
|
BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
|
|
break;
|
|
default:
|
|
std::cerr << "Return type of call instruction not handled: " << I;
|
|
abort ();
|
|
}
|
|
}
|
|
|
|
void V8ISel::visitReturnInst(ReturnInst &I) {
|
|
if (I.getNumOperands () == 1) {
|
|
unsigned RetValReg = getReg (I.getOperand (0));
|
|
switch (getClass (I.getOperand (0)->getType ())) {
|
|
case cByte:
|
|
case cShort:
|
|
case cInt:
|
|
// Schlep it over into i0 (where it will become o0 after restore).
|
|
BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
|
|
break;
|
|
default:
|
|
std::cerr << "Return instruction of this type not handled: " << I;
|
|
abort ();
|
|
}
|
|
}
|
|
|
|
// Just emit a 'retl' instruction to return.
|
|
BuildMI(BB, V8::RETL, 0);
|
|
return;
|
|
}
|
|
|
|
static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
|
|
Function::iterator I = BB; ++I; // Get iterator to next block
|
|
return I != BB->getParent()->end() ? &*I : 0;
|
|
}
|
|
|
|
/// visitBranchInst - Handles conditional and unconditional branches.
|
|
///
|
|
void V8ISel::visitBranchInst(BranchInst &I) {
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor (MBBMap[I.getSuccessor(0)]);
|
|
if (I.isConditional())
|
|
BB->addSuccessor (MBBMap[I.getSuccessor(1)]);
|
|
|
|
BasicBlock *NextBB = getBlockAfter(I.getParent()); // BB after current one
|
|
|
|
BasicBlock *takenSucc = I.getSuccessor (0);
|
|
if (!I.isConditional()) { // Unconditional branch?
|
|
if (I.getSuccessor(0) != NextBB)
|
|
BuildMI (BB, V8::BA, 1).addMBB (MBBMap[takenSucc]);
|
|
return;
|
|
}
|
|
|
|
unsigned CondReg = getReg (I.getCondition ());
|
|
BasicBlock *notTakenSucc = I.getSuccessor (1);
|
|
// Set Z condition code if CondReg was false
|
|
BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
|
|
if (notTakenSucc == NextBB) {
|
|
if (takenSucc != NextBB)
|
|
BuildMI (BB, V8::BNE, 1).addMBB (MBBMap[takenSucc]);
|
|
} else {
|
|
BuildMI (BB, V8::BE, 1).addMBB (MBBMap[notTakenSucc]);
|
|
if (takenSucc != NextBB)
|
|
BuildMI (BB, V8::BA, 1).addMBB (MBBMap[takenSucc]);
|
|
}
|
|
}
|
|
|
|
/// emitGEPOperation - Common code shared between visitGetElementPtrInst and
|
|
/// constant expression GEP support.
|
|
///
|
|
void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator IP,
|
|
Value *Src, User::op_iterator IdxBegin,
|
|
User::op_iterator IdxEnd, unsigned TargetReg) {
|
|
const TargetData &TD = TM.getTargetData ();
|
|
const Type *Ty = Src->getType ();
|
|
unsigned basePtrReg = getReg (Src);
|
|
|
|
// GEPs have zero or more indices; we must perform a struct access
|
|
// or array access for each one.
|
|
for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
|
|
++oi) {
|
|
Value *idx = *oi;
|
|
unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
|
|
if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
|
|
// It's a struct access. idx is the index into the structure,
|
|
// which names the field. Use the TargetData structure to
|
|
// pick out what the layout of the structure is in memory.
|
|
// Use the (constant) structure index's value to find the
|
|
// right byte offset from the StructLayout class's list of
|
|
// structure member offsets.
|
|
unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
|
|
unsigned memberOffset =
|
|
TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
|
|
// Emit an ADD to add memberOffset to the basePtr.
|
|
BuildMI (*MBB, IP, V8::ADDri, 2,
|
|
nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
|
|
// The next type is the member of the structure selected by the
|
|
// index.
|
|
Ty = StTy->getElementType (fieldIndex);
|
|
} else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
|
|
// It's an array or pointer access: [ArraySize x ElementType].
|
|
// We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
|
|
// must find the size of the pointed-to type (Not coincidentally, the next
|
|
// type is the type of the elements in the array).
|
|
Ty = SqTy->getElementType ();
|
|
unsigned elementSize = TD.getTypeSize (Ty);
|
|
unsigned idxReg = getReg (idx, MBB, IP);
|
|
unsigned OffsetReg = makeAnotherReg (Type::IntTy);
|
|
unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
|
|
BuildMI (*MBB, IP, V8::ORri, 2,
|
|
elementSizeReg).addZImm (elementSize).addReg (V8::G0);
|
|
// Emit a SMUL to multiply the register holding the index by
|
|
// elementSize, putting the result in OffsetReg.
|
|
BuildMI (*MBB, IP, V8::SMULrr, 2,
|
|
OffsetReg).addReg (elementSizeReg).addReg (idxReg);
|
|
// Emit an ADD to add OffsetReg to the basePtr.
|
|
BuildMI (*MBB, IP, V8::ADDrr, 2,
|
|
nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
|
|
}
|
|
basePtrReg = nextBasePtrReg;
|
|
}
|
|
// After we have processed all the indices, the result is left in
|
|
// basePtrReg. Move it to the register where we were expected to
|
|
// put the answer.
|
|
BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
|
|
}
|
|
|
|
void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
|
|
unsigned outputReg = getReg (I);
|
|
emitGEPOperation (BB, BB->end (), I.getOperand (0),
|
|
I.op_begin ()+1, I.op_end (), outputReg);
|
|
}
|
|
|
|
|
|
void V8ISel::visitBinaryOperator (Instruction &I) {
|
|
unsigned DestReg = getReg (I);
|
|
unsigned Op0Reg = getReg (I.getOperand (0));
|
|
unsigned Op1Reg = getReg (I.getOperand (1));
|
|
|
|
unsigned ResultReg = DestReg;
|
|
if (getClassB(I.getType()) != cInt)
|
|
ResultReg = makeAnotherReg (I.getType ());
|
|
unsigned OpCase = ~0;
|
|
|
|
// FIXME: support long, ulong, fp.
|
|
switch (I.getOpcode ()) {
|
|
case Instruction::Add: OpCase = 0; break;
|
|
case Instruction::Sub: OpCase = 1; break;
|
|
case Instruction::Mul: OpCase = 2; break;
|
|
case Instruction::And: OpCase = 3; break;
|
|
case Instruction::Or: OpCase = 4; break;
|
|
case Instruction::Xor: OpCase = 5; break;
|
|
case Instruction::Shl: OpCase = 6; break;
|
|
case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
|
|
|
|
case Instruction::Div:
|
|
case Instruction::Rem: {
|
|
unsigned Dest = ResultReg;
|
|
if (I.getOpcode() == Instruction::Rem)
|
|
Dest = makeAnotherReg(I.getType());
|
|
|
|
// FIXME: this is probably only right for 32 bit operands.
|
|
if (I.getType ()->isSigned()) {
|
|
unsigned Tmp = makeAnotherReg (I.getType ());
|
|
// Sign extend into the Y register
|
|
BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
|
|
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
|
|
BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
|
|
} else {
|
|
// Zero extend into the Y register, ie, just set it to zero
|
|
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
|
|
BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
|
|
}
|
|
|
|
if (I.getOpcode() == Instruction::Rem) {
|
|
unsigned Tmp = makeAnotherReg (I.getType ());
|
|
BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
|
|
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
visitInstruction (I);
|
|
return;
|
|
}
|
|
|
|
if (OpCase != ~0U) {
|
|
static const unsigned Opcodes[] = {
|
|
V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
|
|
V8::SLLrr, V8::SRLrr, V8::SRArr
|
|
};
|
|
BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
|
|
}
|
|
|
|
switch (getClass (I.getType ())) {
|
|
case cByte:
|
|
if (I.getType ()->isSigned ()) { // add byte
|
|
BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
|
|
} else { // add ubyte
|
|
unsigned TmpReg = makeAnotherReg (I.getType ());
|
|
BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
|
|
BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
|
|
}
|
|
break;
|
|
case cShort:
|
|
if (I.getType ()->isSigned ()) { // add short
|
|
unsigned TmpReg = makeAnotherReg (I.getType ());
|
|
BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
|
|
BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
|
|
} else { // add ushort
|
|
unsigned TmpReg = makeAnotherReg (I.getType ());
|
|
BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
|
|
BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
|
|
}
|
|
break;
|
|
case cInt:
|
|
// Nothing todo here.
|
|
break;
|
|
default:
|
|
visitInstruction (I);
|
|
return;
|
|
}
|
|
}
|
|
|
|
void V8ISel::visitSetCondInst(Instruction &I) {
|
|
unsigned Op0Reg = getReg (I.getOperand (0));
|
|
unsigned Op1Reg = getReg (I.getOperand (1));
|
|
unsigned DestReg = getReg (I);
|
|
const Type *Ty = I.getOperand (0)->getType ();
|
|
|
|
// Compare the two values.
|
|
BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
|
|
|
|
unsigned BranchIdx;
|
|
switch (I.getOpcode()) {
|
|
default: assert(0 && "Unknown setcc instruction!");
|
|
case Instruction::SetEQ: BranchIdx = 0; break;
|
|
case Instruction::SetNE: BranchIdx = 1; break;
|
|
case Instruction::SetLT: BranchIdx = 2; break;
|
|
case Instruction::SetGT: BranchIdx = 3; break;
|
|
case Instruction::SetLE: BranchIdx = 4; break;
|
|
case Instruction::SetGE: BranchIdx = 5; break;
|
|
}
|
|
static unsigned OpcodeTab[12] = {
|
|
// LLVM SparcV8
|
|
// unsigned signed
|
|
V8::BE, V8::BE, // seteq = be be
|
|
V8::BNE, V8::BNE, // setne = bne bne
|
|
V8::BCS, V8::BL, // setlt = bcs bl
|
|
V8::BGU, V8::BG, // setgt = bgu bg
|
|
V8::BLEU, V8::BLE, // setle = bleu ble
|
|
V8::BCC, V8::BGE // setge = bcc bge
|
|
};
|
|
unsigned Opcode = OpcodeTab[BranchIdx + (Ty->isSigned() ? 1 : 0)];
|
|
MachineBasicBlock *Copy1MBB, *Copy0MBB, *CopyCondMBB;
|
|
MachineBasicBlock::iterator IP;
|
|
#if 0
|
|
// Cond. Branch from BB --> either Copy1MBB or Copy0MBB --> CopyCondMBB
|
|
// Then once we're done with the SetCC, BB = CopyCondMBB.
|
|
BasicBlock *LLVM_BB = BB.getBasicBlock ();
|
|
unsigned Cond0Reg = makeAnotherReg (I.getType ());
|
|
unsigned Cond1Reg = makeAnotherReg (I.getType ());
|
|
F->getBasicBlockList ().push_back (Copy1MBB = new MachineBasicBlock (LLVM_BB));
|
|
F->getBasicBlockList ().push_back (Copy0MBB = new MachineBasicBlock (LLVM_BB));
|
|
F->getBasicBlockList ().push_back (CopyCondMBB = new MachineBasicBlock (LLVM_BB));
|
|
BuildMI (BB, Opcode, 1).addMBB (Copy1MBB);
|
|
BuildMI (BB, V8::BA, 1).addMBB (Copy0MBB);
|
|
IP = Copy1MBB->begin ();
|
|
BuildMI (*Copy1MBB, IP, V8::ORri, 2, Cond1Reg).addZImm (1).addReg (V8::G0);
|
|
BuildMI (*Copy1MBB, IP, V8::BA, 1).addMBB (CopyCondMBB);
|
|
IP = Copy0MBB->begin ();
|
|
BuildMI (*Copy0MBB, IP, V8::ORri, 2, Cond0Reg).addZImm (0).addReg (V8::G0);
|
|
BuildMI (*Copy0MBB, IP, V8::BA, 1).addMBB (CopyCondMBB);
|
|
// What should go in CopyCondMBB: PHI, then OR to copy cond. reg to DestReg
|
|
#endif
|
|
visitInstruction(I);
|
|
}
|
|
|
|
|
|
|
|
/// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
|
|
/// function, lowering any calls to unknown intrinsic functions into the
|
|
/// equivalent LLVM code.
|
|
void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
|
|
for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
|
|
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
|
|
if (CallInst *CI = dyn_cast<CallInst>(I++))
|
|
if (Function *F = CI->getCalledFunction())
|
|
switch (F->getIntrinsicID()) {
|
|
case Intrinsic::not_intrinsic: break;
|
|
default:
|
|
// All other intrinsic calls we must lower.
|
|
Instruction *Before = CI->getPrev();
|
|
TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
|
|
if (Before) { // Move iterator to instruction after call
|
|
I = Before; ++I;
|
|
} else {
|
|
I = BB->begin();
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
|
|
unsigned TmpReg1, TmpReg2;
|
|
switch (ID) {
|
|
default: assert(0 && "Intrinsic not supported!");
|
|
}
|
|
}
|