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https://github.com/c64scene-ar/llvm-6502.git
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c4ce78e261
Summary: This is because the FP64A the hardware will redirect 32-bit reads/writes from/to odd-numbered registers to the upper 32-bits of the corresponding even register. In effect, simulating FR=0 mode when FR=0 mode is not available. Unfortunately, we have to make the decision to avoid mfc1/mtc1 before register allocation so we currently do this for even registers too. FPXX has a similar requirement on 32-bit architectures that lack mfhc1/mthc1 so this patch also handles the affected moves from the FPU for FPXX too. Moves to the FPU were supported by an earlier commit. Differential Revision: http://reviews.llvm.org/D4484 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212938 91177308-0d34-0410-b5e6-96231b3b80d8
149 lines
4.0 KiB
C++
149 lines
4.0 KiB
C++
//===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsMachineFunction.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "MipsInstrInfo.h"
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#include "MipsSubtarget.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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static cl::opt<bool>
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FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
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cl::desc("Always use $gp as the global base register."));
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// class MipsCallEntry.
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MipsCallEntry::MipsCallEntry(const StringRef &N) {
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#ifndef NDEBUG
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Name = N;
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Val = nullptr;
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#endif
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}
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MipsCallEntry::MipsCallEntry(const GlobalValue *V) {
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#ifndef NDEBUG
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Val = V;
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#endif
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}
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bool MipsCallEntry::isConstant(const MachineFrameInfo *) const {
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return false;
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}
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bool MipsCallEntry::isAliased(const MachineFrameInfo *) const {
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return false;
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}
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bool MipsCallEntry::mayAlias(const MachineFrameInfo *) const {
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return false;
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}
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void MipsCallEntry::printCustom(raw_ostream &O) const {
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O << "MipsCallEntry: ";
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#ifndef NDEBUG
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if (Val)
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O << Val->getName();
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else
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O << Name;
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#endif
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}
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MipsFunctionInfo::~MipsFunctionInfo() {
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for (StringMap<const MipsCallEntry *>::iterator
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I = ExternalCallEntries.begin(), E = ExternalCallEntries.end(); I != E;
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++I)
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delete I->getValue();
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for (const auto &Entry : GlobalCallEntries)
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delete Entry.second;
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}
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bool MipsFunctionInfo::globalBaseRegSet() const {
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return GlobalBaseReg;
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}
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unsigned MipsFunctionInfo::getGlobalBaseReg() {
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// Return if it has already been initialized.
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if (GlobalBaseReg)
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return GlobalBaseReg;
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const MipsSubtarget &ST = MF.getTarget().getSubtarget<MipsSubtarget>();
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const TargetRegisterClass *RC;
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if (ST.inMips16Mode())
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RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
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else
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RC = ST.isABI_N64() ?
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(const TargetRegisterClass*)&Mips::GPR64RegClass :
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(const TargetRegisterClass*)&Mips::GPR32RegClass;
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return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
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}
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bool MipsFunctionInfo::mips16SPAliasRegSet() const {
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return Mips16SPAliasReg;
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}
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unsigned MipsFunctionInfo::getMips16SPAliasReg() {
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// Return if it has already been initialized.
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if (Mips16SPAliasReg)
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return Mips16SPAliasReg;
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const TargetRegisterClass *RC;
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RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
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return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC);
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}
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void MipsFunctionInfo::createEhDataRegsFI() {
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for (int I = 0; I < 4; ++I) {
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const MipsSubtarget &ST = MF.getTarget().getSubtarget<MipsSubtarget>();
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const TargetRegisterClass *RC = ST.isABI_N64() ?
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&Mips::GPR64RegClass : &Mips::GPR32RegClass;
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EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
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RC->getAlignment(), false);
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}
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}
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bool MipsFunctionInfo::isEhDataRegFI(int FI) const {
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return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
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|| FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
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}
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MachinePointerInfo MipsFunctionInfo::callPtrInfo(const StringRef &Name) {
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const MipsCallEntry *&E = ExternalCallEntries[Name];
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if (!E)
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E = new MipsCallEntry(Name);
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return MachinePointerInfo(E);
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}
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MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *Val) {
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const MipsCallEntry *&E = GlobalCallEntries[Val];
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if (!E)
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E = new MipsCallEntry(Val);
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return MachinePointerInfo(E);
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}
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int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
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if (MoveF64ViaSpillFI == -1) {
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MoveF64ViaSpillFI = MF.getFrameInfo()->CreateStackObject(
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RC->getSize(), RC->getAlignment(), false);
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}
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return MoveF64ViaSpillFI;
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}
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void MipsFunctionInfo::anchor() { }
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