Andrew Trick 0a39d4e4c8 misched: Added ScoreboardHazardRecognizer. ... The Hazard checker implements in-order contraints, or interlocked resources. Ready instructions with hazards do not enter the available queue and are not visible to other heuristics. The major code change is the addition of SchedBoundary to encapsulate the state at the top or bottom of the schedule, including both a pending and available queue. The scheduler now counts cycles in sync with the hazard checker. These are minimum cycle counts based on known hazards. Targets with no itinerary (x86_64) currently remain at cycle 0. To fix this, we need to provide some maximum issue width for all targets. We also need to add the concept of expected latency vs. minimum latency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157427 91177308-0d34-0410-b5e6-96231b3b80d8		2012-05-24 22:11:09 +00:00
..
Analysis	Mark some static arrays as const.	2012-05-24 06:35:32 +00:00
Archive
AsmParser	Silence Clang's -Wlogical-op-parentheses warning.	2012-05-24 17:11:00 +00:00
Bitcode
CodeGen	misched: Added ScoreboardHazardRecognizer.	2012-05-24 22:11:09 +00:00
DebugInfo
ExecutionEngine
Linker
MC	Mark some static arrays as const.	2012-05-24 06:35:32 +00:00
Object	Mark some static arrays as const.	2012-05-24 06:35:32 +00:00
Support	Remove the PTX back-end and all of its artifacts (triple, etc.)	2012-05-24 21:38:21 +00:00
TableGen
Target	Remove the PTX back-end and all of its artifacts (triple, etc.)	2012-05-24 21:38:21 +00:00
Transforms	PR1255 related changes (case ranges):	2012-05-24 09:33:20 +00:00
VMCore	Add half support to LLVM (for OpenCL)	2012-05-24 15:59:06 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile