Bill Schmidt 202b6045bf [PowerPC] Implement the vclz instructions for PWR8 ... Patch by Kit Barton. Add the vector count leading zeros instruction for byte, halfword, word, and doubleword sizes. This is a fairly straightforward addition after the changes made for vpopcnt: 1. Add the correct definitions for the various instructions in PPCInstrAltivec.td 2. Make the CTLZ operation legal on vector types when using P8Altivec in PPCISelLowering.cpp Test Plan Created new test case in test/CodeGen/PowerPC/vec_clz.ll to check the instructions are being generated when the CTLZ operation is used in LLVM. Check the encoding and decoding in test/MC/PowerPC/ppc_encoding_vmx.s and test/Disassembler/PowerPC/ppc_encoding_vmx.txt respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228301 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-05 15:24:47 +00:00
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Disassembler	[PowerPC] Implement the vclz instructions for PWR8	2015-02-05 15:24:47 +00:00
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PowerPC	[PowerPC] Implement the vclz instructions for PWR8	2015-02-05 15:24:47 +00:00
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