mirror of
https://github.com/c64scene-ar/llvm-6502.git
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87773c318f
Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
2.7 KiB
ArmAsm
58 lines
2.7 KiB
ArmAsm
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
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// Check that the assembler can handle the documented syntax for AArch64
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//------------------------------------------------------------------------------
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// Vector Integer Rounding Shift Lef (Signed)
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//------------------------------------------------------------------------------
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srshl v0.8b, v1.8b, v2.8b
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srshl v0.16b, v1.16b, v2.16b
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srshl v0.4h, v1.4h, v2.4h
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srshl v0.8h, v1.8h, v2.8h
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srshl v0.2s, v1.2s, v2.2s
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srshl v0.4s, v1.4s, v2.4s
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srshl v0.2d, v1.2d, v2.2d
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// CHECK: srshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x54,0x22,0x0e]
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// CHECK: srshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x54,0x22,0x4e]
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// CHECK: srshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x54,0x62,0x0e]
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// CHECK: srshl v0.8h, v1.8h, v2.8h // encoding: [0x20,0x54,0x62,0x4e]
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// CHECK: srshl v0.2s, v1.2s, v2.2s // encoding: [0x20,0x54,0xa2,0x0e]
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// CHECK: srshl v0.4s, v1.4s, v2.4s // encoding: [0x20,0x54,0xa2,0x4e]
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// CHECK: srshl v0.2d, v1.2d, v2.2d // encoding: [0x20,0x54,0xe2,0x4e]
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//------------------------------------------------------------------------------
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// Vector Integer Rounding Shift Lef (Unsigned)
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//------------------------------------------------------------------------------
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urshl v0.8b, v1.8b, v2.8b
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urshl v0.16b, v1.16b, v2.16b
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urshl v0.4h, v1.4h, v2.4h
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urshl v0.8h, v1.8h, v2.8h
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urshl v0.2s, v1.2s, v2.2s
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urshl v0.4s, v1.4s, v2.4s
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urshl v0.2d, v1.2d, v2.2d
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// CHECK: urshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x54,0x22,0x2e]
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// CHECK: urshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x54,0x22,0x6e]
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// CHECK: urshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x54,0x62,0x2e]
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// CHECK: urshl v0.8h, v1.8h, v2.8h // encoding: [0x20,0x54,0x62,0x6e]
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// CHECK: urshl v0.2s, v1.2s, v2.2s // encoding: [0x20,0x54,0xa2,0x2e]
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// CHECK: urshl v0.4s, v1.4s, v2.4s // encoding: [0x20,0x54,0xa2,0x6e]
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// CHECK: urshl v0.2d, v1.2d, v2.2d // encoding: [0x20,0x54,0xe2,0x6e]
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//------------------------------------------------------------------------------
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// Scalar Integer Rounding Shift Lef (Signed)
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//------------------------------------------------------------------------------
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srshl d17, d31, d8
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// CHECK: srshl d17, d31, d8 // encoding: [0xf1,0x57,0xe8,0x5e]
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//------------------------------------------------------------------------------
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// Scalar Integer Rounding Shift Lef (Unsigned)
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//------------------------------------------------------------------------------
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urshl d17, d31, d8
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// CHECK: urshl d17, d31, d8 // encoding: [0xf1,0x57,0xe8,0x7e]
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