mirror of
https://github.com/c64scene-ar/llvm-6502.git
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3bf9125933
addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
104 lines
4.0 KiB
C++
104 lines
4.0 KiB
C++
//===- MSP430InstrInfo.h - MSP430 Instruction Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MSP430 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_MSP430INSTRINFO_H
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#define LLVM_TARGET_MSP430INSTRINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "MSP430RegisterInfo.h"
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namespace llvm {
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class MSP430TargetMachine;
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/// MSP430II - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace MSP430II {
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enum {
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SizeShift = 2,
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SizeMask = 7 << SizeShift,
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SizeUnknown = 0 << SizeShift,
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SizeSpecial = 1 << SizeShift,
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Size2Bytes = 2 << SizeShift,
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Size4Bytes = 3 << SizeShift,
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Size6Bytes = 4 << SizeShift
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};
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}
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class MSP430InstrInfo : public TargetInstrInfoImpl {
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const MSP430RegisterInfo RI;
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MSP430TargetMachine &TM;
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public:
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explicit MSP430InstrInfo(MSP430TargetMachine &TM);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
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bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC,
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DebugLoc DL) const;
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bool isMoveInstr(const MachineInstr& MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill,
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int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const;
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virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const;
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unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
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// Branch folding goodness
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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bool isUnpredicatedTerminator(const MachineInstr *MI) const;
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bool AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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};
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}
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#endif
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