mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 16:30:00 +00:00
54c78ef2fe
will not accept negative values for these. LLVM's default operand printing sign extends values, so that valid unsigned values appear as negative immediates. Print all VMOV immediate operands as hex values to resolve this. Radar 7372576. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86301 91177308-0d34-0410-b5e6-96231b3b80d8
324 lines
9.0 KiB
LLVM
324 lines
9.0 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @v_movi8() nounwind {
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;CHECK: v_movi8:
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;CHECK: vmov.i8
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ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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define <4 x i16> @v_movi16a() nounwind {
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;CHECK: v_movi16a:
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;CHECK: vmov.i16
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ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
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}
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; 0x1000 = 4096
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define <4 x i16> @v_movi16b() nounwind {
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;CHECK: v_movi16b:
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;CHECK: vmov.i16
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ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
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}
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define <2 x i32> @v_movi32a() nounwind {
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;CHECK: v_movi32a:
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;CHECK: vmov.i32
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ret <2 x i32> < i32 32, i32 32 >
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}
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; 0x2000 = 8192
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define <2 x i32> @v_movi32b() nounwind {
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;CHECK: v_movi32b:
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;CHECK: vmov.i32
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ret <2 x i32> < i32 8192, i32 8192 >
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}
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; 0x200000 = 2097152
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define <2 x i32> @v_movi32c() nounwind {
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;CHECK: v_movi32c:
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;CHECK: vmov.i32
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ret <2 x i32> < i32 2097152, i32 2097152 >
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}
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; 0x20000000 = 536870912
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define <2 x i32> @v_movi32d() nounwind {
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;CHECK: v_movi32d:
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;CHECK: vmov.i32
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ret <2 x i32> < i32 536870912, i32 536870912 >
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}
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; 0x20ff = 8447
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define <2 x i32> @v_movi32e() nounwind {
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;CHECK: v_movi32e:
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;CHECK: vmov.i32
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ret <2 x i32> < i32 8447, i32 8447 >
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}
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; 0x20ffff = 2162687
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define <2 x i32> @v_movi32f() nounwind {
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;CHECK: v_movi32f:
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;CHECK: vmov.i32
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ret <2 x i32> < i32 2162687, i32 2162687 >
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}
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; 0xff0000ff0000ffff = 18374687574888349695
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define <1 x i64> @v_movi64() nounwind {
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;CHECK: v_movi64:
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;CHECK: vmov.i64
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ret <1 x i64> < i64 18374687574888349695 >
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}
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define <16 x i8> @v_movQi8() nounwind {
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;CHECK: v_movQi8:
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;CHECK: vmov.i8
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ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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define <8 x i16> @v_movQi16a() nounwind {
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;CHECK: v_movQi16a:
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;CHECK: vmov.i16
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ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
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}
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; 0x1000 = 4096
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define <8 x i16> @v_movQi16b() nounwind {
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;CHECK: v_movQi16b:
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;CHECK: vmov.i16
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ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
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}
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define <4 x i32> @v_movQi32a() nounwind {
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;CHECK: v_movQi32a:
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;CHECK: vmov.i32
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ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
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}
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; 0x2000 = 8192
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define <4 x i32> @v_movQi32b() nounwind {
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;CHECK: v_movQi32b:
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;CHECK: vmov.i32
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ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
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}
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; 0x200000 = 2097152
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define <4 x i32> @v_movQi32c() nounwind {
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;CHECK: v_movQi32c:
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;CHECK: vmov.i32
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ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
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}
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; 0x20000000 = 536870912
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define <4 x i32> @v_movQi32d() nounwind {
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;CHECK: v_movQi32d:
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;CHECK: vmov.i32
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ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
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}
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; 0x20ff = 8447
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define <4 x i32> @v_movQi32e() nounwind {
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;CHECK: v_movQi32e:
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;CHECK: vmov.i32
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ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
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}
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; 0x20ffff = 2162687
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define <4 x i32> @v_movQi32f() nounwind {
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;CHECK: v_movQi32f:
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;CHECK: vmov.i32
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ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
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}
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; 0xff0000ff0000ffff = 18374687574888349695
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define <2 x i64> @v_movQi64() nounwind {
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;CHECK: v_movQi64:
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;CHECK: vmov.i64
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ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
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}
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; Check for correct assembler printing for immediate values.
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%struct.int8x8_t = type { <8 x i8> }
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define arm_apcscc void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
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entry:
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;CHECK: vdupn128:
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;CHECK: vmov.i8 d0, #0x80
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%0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
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store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8
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ret void
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}
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define arm_apcscc void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
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entry:
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;CHECK: vdupnneg75:
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;CHECK: vmov.i8 d0, #0xB5
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%0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
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store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8
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ret void
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}
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define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
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;CHECK: vmovls8:
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;CHECK: vmovl.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vmovls.v8i16(<8 x i8> %tmp1)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
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;CHECK: vmovls16:
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;CHECK: vmovl.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
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;CHECK: vmovls32:
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;CHECK: vmovl.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vmovls.v2i64(<2 x i32> %tmp1)
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ret <2 x i64> %tmp2
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}
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define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
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;CHECK: vmovlu8:
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;CHECK: vmovl.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vmovlu.v8i16(<8 x i8> %tmp1)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
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;CHECK: vmovlu16:
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;CHECK: vmovl.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vmovlu.v4i32(<4 x i16> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
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;CHECK: vmovlu32:
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;CHECK: vmovl.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vmovlu.v2i64(<2 x i32> %tmp1)
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ret <2 x i64> %tmp2
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}
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declare <8 x i16> @llvm.arm.neon.vmovls.v8i16(<8 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vmovls.v2i64(<2 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vmovlu.v8i16(<8 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vmovlu.v4i32(<4 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vmovlu.v2i64(<2 x i32>) nounwind readnone
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define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
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;CHECK: vmovni16:
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;CHECK: vmovn.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vmovn.v8i8(<8 x i16> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
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;CHECK: vmovni32:
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;CHECK: vmovn.i32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vmovn.v4i16(<4 x i32> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
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;CHECK: vmovni64:
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;CHECK: vmovn.i64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vmovn.v2i32(<2 x i64> %tmp1)
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ret <2 x i32> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vmovn.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vmovn.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vmovn.v2i32(<2 x i64>) nounwind readnone
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define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
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;CHECK: vqmovns16:
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;CHECK: vqmovn.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
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;CHECK: vqmovns32:
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;CHECK: vqmovn.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
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;CHECK: vqmovns64:
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;CHECK: vqmovn.s64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
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;CHECK: vqmovnu16:
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;CHECK: vqmovn.u16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
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;CHECK: vqmovnu32:
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;CHECK: vqmovn.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
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;CHECK: vqmovnu64:
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;CHECK: vqmovn.u64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
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;CHECK: vqmovuns16:
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;CHECK: vqmovun.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
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;CHECK: vqmovuns32:
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;CHECK: vqmovun.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
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;CHECK: vqmovuns64:
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;CHECK: vqmovun.s64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
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ret <2 x i32> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
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