mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
152 lines
4.0 KiB
LLVM
152 lines
4.0 KiB
LLVM
; Test 128-bit floating-point loads.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check loads with no offset.
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define double @f1(i64 %src) {
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; CHECK-LABEL: f1:
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; CHECK: ld %f0, 0(%r2)
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; CHECK: ld %f2, 8(%r2)
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; CHECK: br %r14
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%ptr = inttoptr i64 %src to fp128 *
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%val = load fp128 , fp128 *%ptr
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%trunc = fptrunc fp128 %val to double
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ret double %trunc
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}
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; Check the highest aligned offset that allows LD for both halves.
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define double @f2(i64 %src) {
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; CHECK-LABEL: f2:
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; CHECK: ld %f0, 4080(%r2)
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; CHECK: ld %f2, 4088(%r2)
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; CHECK: br %r14
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%add = add i64 %src, 4080
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%ptr = inttoptr i64 %add to fp128 *
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%val = load fp128 , fp128 *%ptr
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%trunc = fptrunc fp128 %val to double
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ret double %trunc
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}
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; Check the next doubleword up, which requires a mixture of LD and LDY.
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define double @f3(i64 %src) {
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; CHECK-LABEL: f3:
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; CHECK: ld %f0, 4088(%r2)
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; CHECK: ldy %f2, 4096(%r2)
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; CHECK: br %r14
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%add = add i64 %src, 4088
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%ptr = inttoptr i64 %add to fp128 *
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%val = load fp128 , fp128 *%ptr
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%trunc = fptrunc fp128 %val to double
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ret double %trunc
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}
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; Check the next doubleword after that, which requires LDY for both halves.
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define double @f4(i64 %src) {
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; CHECK-LABEL: f4:
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; CHECK: ldy %f0, 4096(%r2)
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; CHECK: ldy %f2, 4104(%r2)
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; CHECK: br %r14
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%add = add i64 %src, 4096
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%ptr = inttoptr i64 %add to fp128 *
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%val = load fp128 , fp128 *%ptr
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%trunc = fptrunc fp128 %val to double
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ret double %trunc
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}
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; Check the highest aligned offset that allows LDY for both halves.
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define double @f5(i64 %src) {
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; CHECK-LABEL: f5:
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; CHECK: ldy %f0, 524272(%r2)
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; CHECK: ldy %f2, 524280(%r2)
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; CHECK: br %r14
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%add = add i64 %src, 524272
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%ptr = inttoptr i64 %add to fp128 *
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%val = load fp128 , fp128 *%ptr
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%trunc = fptrunc fp128 %val to double
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ret double %trunc
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}
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; Check the next doubleword up, which requires separate address logic.
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; Other sequences besides this one would be OK.
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define double @f6(i64 %src) {
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; CHECK-LABEL: f6:
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; CHECK: lay %r1, 524280(%r2)
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; CHECK: ld %f0, 0(%r1)
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; CHECK: ld %f2, 8(%r1)
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; CHECK: br %r14
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%add = add i64 %src, 524280
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%ptr = inttoptr i64 %add to fp128 *
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%val = load fp128 , fp128 *%ptr
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%trunc = fptrunc fp128 %val to double
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ret double %trunc
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}
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; Check the highest aligned negative offset, which needs a combination of
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; LDY and LD.
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define double @f7(i64 %src) {
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; CHECK-LABEL: f7:
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; CHECK: ldy %f0, -8(%r2)
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; CHECK: ld %f2, 0(%r2)
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; CHECK: br %r14
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%add = add i64 %src, -8
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%ptr = inttoptr i64 %add to fp128 *
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%val = load fp128 , fp128 *%ptr
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%trunc = fptrunc fp128 %val to double
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ret double %trunc
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}
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; Check the next doubleword down, which requires LDY for both halves.
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define double @f8(i64 %src) {
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; CHECK-LABEL: f8:
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; CHECK: ldy %f0, -16(%r2)
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; CHECK: ldy %f2, -8(%r2)
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; CHECK: br %r14
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%add = add i64 %src, -16
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%ptr = inttoptr i64 %add to fp128 *
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%val = load fp128 , fp128 *%ptr
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%trunc = fptrunc fp128 %val to double
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ret double %trunc
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}
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; Check the lowest offset that allows LDY for both halves.
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define double @f9(i64 %src) {
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; CHECK-LABEL: f9:
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; CHECK: ldy %f0, -524288(%r2)
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; CHECK: ldy %f2, -524280(%r2)
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; CHECK: br %r14
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%add = add i64 %src, -524288
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%ptr = inttoptr i64 %add to fp128 *
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%val = load fp128 , fp128 *%ptr
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%trunc = fptrunc fp128 %val to double
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ret double %trunc
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}
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; Check the next doubleword down, which requires separate address logic.
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; Other sequences besides this one would be OK.
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define double @f10(i64 %src) {
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; CHECK-LABEL: f10:
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; CHECK: agfi %r2, -524296
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; CHECK: ld %f0, 0(%r2)
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; CHECK: ld %f2, 8(%r2)
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; CHECK: br %r14
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%add = add i64 %src, -524296
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%ptr = inttoptr i64 %add to fp128 *
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%val = load fp128 , fp128 *%ptr
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%trunc = fptrunc fp128 %val to double
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ret double %trunc
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}
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; Check that indices are allowed.
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define double @f11(i64 %src, i64 %index) {
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; CHECK-LABEL: f11:
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; CHECK: ld %f0, 4088({{%r2,%r3|%r3,%r2}})
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; CHECK: ldy %f2, 4096({{%r2,%r3|%r3,%r2}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4088
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%ptr = inttoptr i64 %add2 to fp128 *
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%val = load fp128 , fp128 *%ptr
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%trunc = fptrunc fp128 %val to double
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ret double %trunc
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}
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