mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
120 lines
3.4 KiB
LLVM
120 lines
3.4 KiB
LLVM
; Test multiplication of two f32s, producing an f32 result.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare float @foo()
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; Check register multiplication.
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define float @f1(float %f1, float %f2) {
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; CHECK-LABEL: f1:
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; CHECK: meebr %f0, %f2
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; CHECK: br %r14
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%res = fmul float %f1, %f2
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ret float %res
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}
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; Check the low end of the MEEB range.
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define float @f2(float %f1, float *%ptr) {
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; CHECK-LABEL: f2:
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; CHECK: meeb %f0, 0(%r2)
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; CHECK: br %r14
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%f2 = load float , float *%ptr
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%res = fmul float %f1, %f2
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ret float %res
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}
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; Check the high end of the aligned MEEB range.
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define float @f3(float %f1, float *%base) {
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; CHECK-LABEL: f3:
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; CHECK: meeb %f0, 4092(%r2)
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; CHECK: br %r14
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%ptr = getelementptr float, float *%base, i64 1023
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%f2 = load float , float *%ptr
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%res = fmul float %f1, %f2
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ret float %res
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define float @f4(float %f1, float *%base) {
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; CHECK-LABEL: f4:
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; CHECK: aghi %r2, 4096
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; CHECK: meeb %f0, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr float, float *%base, i64 1024
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%f2 = load float , float *%ptr
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%res = fmul float %f1, %f2
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ret float %res
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}
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; Check negative displacements, which also need separate address logic.
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define float @f5(float %f1, float *%base) {
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; CHECK-LABEL: f5:
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; CHECK: aghi %r2, -4
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; CHECK: meeb %f0, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr float, float *%base, i64 -1
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%f2 = load float , float *%ptr
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%res = fmul float %f1, %f2
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ret float %res
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}
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; Check that MEEB allows indices.
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define float @f6(float %f1, float *%base, i64 %index) {
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; CHECK-LABEL: f6:
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; CHECK: sllg %r1, %r3, 2
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; CHECK: meeb %f0, 400(%r1,%r2)
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; CHECK: br %r14
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%ptr1 = getelementptr float, float *%base, i64 %index
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%ptr2 = getelementptr float, float *%ptr1, i64 100
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%f2 = load float , float *%ptr2
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%res = fmul float %f1, %f2
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ret float %res
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}
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; Check that multiplications of spilled values can use MEEB rather than MEEBR.
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define float @f7(float *%ptr0) {
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; CHECK-LABEL: f7:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: meeb %f0, 16{{[04]}}(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr float, float *%ptr0, i64 2
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%ptr2 = getelementptr float, float *%ptr0, i64 4
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%ptr3 = getelementptr float, float *%ptr0, i64 6
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%ptr4 = getelementptr float, float *%ptr0, i64 8
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%ptr5 = getelementptr float, float *%ptr0, i64 10
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%ptr6 = getelementptr float, float *%ptr0, i64 12
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%ptr7 = getelementptr float, float *%ptr0, i64 14
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%ptr8 = getelementptr float, float *%ptr0, i64 16
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%ptr9 = getelementptr float, float *%ptr0, i64 18
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%ptr10 = getelementptr float, float *%ptr0, i64 20
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%val0 = load float , float *%ptr0
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%val1 = load float , float *%ptr1
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%val2 = load float , float *%ptr2
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%val3 = load float , float *%ptr3
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%val4 = load float , float *%ptr4
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%val5 = load float , float *%ptr5
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%val6 = load float , float *%ptr6
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%val7 = load float , float *%ptr7
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%val8 = load float , float *%ptr8
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%val9 = load float , float *%ptr9
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%val10 = load float , float *%ptr10
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%ret = call float @foo()
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%mul0 = fmul float %ret, %val0
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%mul1 = fmul float %mul0, %val1
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%mul2 = fmul float %mul1, %val2
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%mul3 = fmul float %mul2, %val3
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%mul4 = fmul float %mul3, %val4
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%mul5 = fmul float %mul4, %val5
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%mul6 = fmul float %mul5, %val6
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%mul7 = fmul float %mul6, %val7
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%mul8 = fmul float %mul7, %val8
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%mul9 = fmul float %mul8, %val9
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%mul10 = fmul float %mul9, %val10
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ret float %mul10
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}
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