mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
181 lines
4.7 KiB
LLVM
181 lines
4.7 KiB
LLVM
; Test additions between an i64 and a zero-extended i32.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i64 @foo()
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; Check ALGFR.
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define i64 @f1(i64 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: algfr %r2, %r3
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; CHECK: br %r14
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check ALGF with no displacement.
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define i64 @f2(i64 %a, i32 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: algf %r2, 0(%r3)
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; CHECK: br %r14
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%b = load i32 , i32 *%src
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check the high end of the aligned ALGF range.
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define i64 @f3(i64 %a, i32 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: algf %r2, 524284(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131071
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%b = load i32 , i32 *%ptr
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f4(i64 %a, i32 *%src) {
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; CHECK-LABEL: f4:
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; CHECK: agfi %r3, 524288
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; CHECK: algf %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131072
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%b = load i32 , i32 *%ptr
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check the high end of the negative aligned ALGF range.
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define i64 @f5(i64 %a, i32 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: algf %r2, -4(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -1
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%b = load i32 , i32 *%ptr
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check the low end of the ALGF range.
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define i64 @f6(i64 %a, i32 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: algf %r2, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131072
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%b = load i32 , i32 *%ptr
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f7(i64 %a, i32 *%src) {
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; CHECK-LABEL: f7:
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; CHECK: agfi %r3, -524292
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; CHECK: algf %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131073
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%b = load i32 , i32 *%ptr
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check that ALGF allows an index.
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define i64 @f8(i64 %a, i64 %src, i64 %index) {
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; CHECK-LABEL: f8:
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; CHECK: algf %r2, 524284({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524284
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%ptr = inttoptr i64 %add2 to i32 *
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%b = load i32 , i32 *%ptr
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check that additions of spilled values can use ALGF rather than ALGFR.
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define i64 @f9(i32 *%ptr0) {
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; CHECK-LABEL: f9:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: algf %r2, 16{{[04]}}(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i32, i32 *%ptr0, i64 2
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%ptr2 = getelementptr i32, i32 *%ptr0, i64 4
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%ptr3 = getelementptr i32, i32 *%ptr0, i64 6
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%ptr4 = getelementptr i32, i32 *%ptr0, i64 8
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%ptr5 = getelementptr i32, i32 *%ptr0, i64 10
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%ptr6 = getelementptr i32, i32 *%ptr0, i64 12
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%ptr7 = getelementptr i32, i32 *%ptr0, i64 14
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%ptr8 = getelementptr i32, i32 *%ptr0, i64 16
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%ptr9 = getelementptr i32, i32 *%ptr0, i64 18
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%val0 = load i32 , i32 *%ptr0
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%val1 = load i32 , i32 *%ptr1
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%val2 = load i32 , i32 *%ptr2
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%val3 = load i32 , i32 *%ptr3
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%val4 = load i32 , i32 *%ptr4
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%val5 = load i32 , i32 *%ptr5
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%val6 = load i32 , i32 *%ptr6
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%val7 = load i32 , i32 *%ptr7
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%val8 = load i32 , i32 *%ptr8
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%val9 = load i32 , i32 *%ptr9
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%frob0 = add i32 %val0, 100
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%frob1 = add i32 %val1, 100
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%frob2 = add i32 %val2, 100
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%frob3 = add i32 %val3, 100
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%frob4 = add i32 %val4, 100
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%frob5 = add i32 %val5, 100
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%frob6 = add i32 %val6, 100
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%frob7 = add i32 %val7, 100
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%frob8 = add i32 %val8, 100
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%frob9 = add i32 %val9, 100
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store i32 %frob0, i32 *%ptr0
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store i32 %frob1, i32 *%ptr1
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store i32 %frob2, i32 *%ptr2
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store i32 %frob3, i32 *%ptr3
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store i32 %frob4, i32 *%ptr4
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store i32 %frob5, i32 *%ptr5
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store i32 %frob6, i32 *%ptr6
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store i32 %frob7, i32 *%ptr7
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store i32 %frob8, i32 *%ptr8
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store i32 %frob9, i32 *%ptr9
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%ret = call i64 @foo()
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%ext0 = zext i32 %frob0 to i64
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%ext1 = zext i32 %frob1 to i64
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%ext2 = zext i32 %frob2 to i64
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%ext3 = zext i32 %frob3 to i64
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%ext4 = zext i32 %frob4 to i64
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%ext5 = zext i32 %frob5 to i64
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%ext6 = zext i32 %frob6 to i64
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%ext7 = zext i32 %frob7 to i64
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%ext8 = zext i32 %frob8 to i64
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%ext9 = zext i32 %frob9 to i64
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%add0 = add i64 %ret, %ext0
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%add1 = add i64 %add0, %ext1
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%add2 = add i64 %add1, %ext2
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%add3 = add i64 %add2, %ext3
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%add4 = add i64 %add3, %ext4
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%add5 = add i64 %add4, %ext5
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%add6 = add i64 %add5, %ext6
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%add7 = add i64 %add6, %ext7
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%add8 = add i64 %add7, %ext8
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%add9 = add i64 %add8, %ext9
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ret i64 %add9
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}
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