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https://github.com/c64scene-ar/llvm-6502.git
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3bea6a4959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226483 91177308-0d34-0410-b5e6-96231b3b80d8
84 lines
2.1 KiB
LLVM
84 lines
2.1 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Verify that ALU32 - aslh, asrh, sxth, sxtb, zxth, zxtb intrinsics
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; are lowered to the right instructions.
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@c = external global i64
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}aslh({{ *}}r{{[0-9]+}}{{ *}})
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define void @test1(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.aslh(i32 %a)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.A2.aslh(i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}asrh({{ *}}r{{[0-9]+}}{{ *}})
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define void @test2(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.asrh(i32 %a)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.A2.asrh(i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}sxtb({{ *}}r{{[0-9]+}}{{ *}})
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define void @test3(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.sxtb(i32 %a)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.A2.sxtb(i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}sxth({{ *}}r{{[0-9]+}}{{ *}})
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define void @test4(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.sxth(i32 %a)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.A2.sxth(i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}zxtb({{ *}}r{{[0-9]+}}{{ *}})
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define void @test6(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.zxtb(i32 %a)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.A2.zxtb(i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}zxth({{ *}}r{{[0-9]+}}{{ *}})
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define void @test7(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.zxth(i32 %a)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.A2.zxth(i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}asrh({{ *}}r{{[0-9]+}}{{ *}})
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define void @test8(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.SI.to.SXTHI.asrh(i32 %a)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.SI.to.SXTHI.asrh(i32) #1
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