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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
31 lines
1.1 KiB
LLVM
31 lines
1.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone
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declare double @llvm.sqrt.f64(double) nounwind readnone
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; FUNC-LABEL: {{^}}rcp_f64:
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; SI: v_rcp_f64_e32
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define void @rcp_f64(double addrspace(1)* %out, double %src) nounwind {
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%rcp = call double @llvm.AMDGPU.rcp.f64(double %src) nounwind readnone
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store double %rcp, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_pat_f64:
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; SI: v_rcp_f64_e32
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define void @rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind {
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%rcp = fdiv double 1.0, %src
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store double %rcp, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}rsq_rcp_pat_f64:
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; SI-UNSAFE: v_rsq_f64_e32
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; SI-SAFE-NOT: v_rsq_f64_e32
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define void @rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind {
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%sqrt = call double @llvm.sqrt.f64(double %src) nounwind readnone
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%rcp = call double @llvm.AMDGPU.rcp.f64(double %sqrt) nounwind readnone
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store double %rcp, double addrspace(1)* %out, align 8
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ret void
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}
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