mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0b8c9a80f2
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
134 lines
4.6 KiB
C++
134 lines
4.6 KiB
C++
//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the NVPTX target.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTXTargetMachine.h"
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#include "MCTargetDesc/NVPTXMCAsmInfo.h"
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#include "NVPTX.h"
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#include "NVPTXAllocaHoisting.h"
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#include "NVPTXLowerAggrCopies.h"
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#include "NVPTXSplitBBatBar.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/Analysis/Passes.h"
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#include "llvm/Analysis/Verifier.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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extern "C" void LLVMInitializeNVPTXTarget() {
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// Register the target.
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RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
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RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
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RegisterMCAsmInfo<NVPTXMCAsmInfo> A(TheNVPTXTarget32);
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RegisterMCAsmInfo<NVPTXMCAsmInfo> B(TheNVPTXTarget64);
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}
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NVPTXTargetMachine::NVPTXTargetMachine(const Target &T,
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StringRef TT,
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StringRef CPU,
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StringRef FS,
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const TargetOptions& Options,
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool is64bit)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, is64bit),
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DL(Subtarget.getDataLayout()),
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InstrInfo(*this), TLInfo(*this), TSInfo(*this), FrameLowering(*this,is64bit),
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STTI(&TLInfo), VTTI(&TLInfo)
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/*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {
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}
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void NVPTXTargetMachine32::anchor() {}
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NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
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}
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void NVPTXTargetMachine64::anchor() {}
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NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
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}
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namespace llvm {
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class NVPTXPassConfig : public TargetPassConfig {
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public:
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NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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NVPTXTargetMachine &getNVPTXTargetMachine() const {
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return getTM<NVPTXTargetMachine>();
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}
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virtual bool addInstSelector();
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virtual bool addPreRegAlloc();
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};
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}
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TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
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NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
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return PassConfig;
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}
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bool NVPTXPassConfig::addInstSelector() {
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addPass(createLowerAggrCopies());
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addPass(createSplitBBatBarPass());
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addPass(createAllocaHoisting());
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addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
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addPass(createVectorElementizePass(getNVPTXTargetMachine()));
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return false;
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}
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bool NVPTXPassConfig::addPreRegAlloc() {
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return false;
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}
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