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https://github.com/c64scene-ar/llvm-6502.git
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0ba0a89c6b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70717 91177308-0d34-0410-b5e6-96231b3b80d8
122 lines
4.5 KiB
TableGen
122 lines
4.5 KiB
TableGen
//===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the MSP430 instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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include "MSP430InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Type Constraints.
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//===----------------------------------------------------------------------===//
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class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
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class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
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//===----------------------------------------------------------------------===//
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// Type Profiles.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MSP430 Specific Node Definitions.
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//===----------------------------------------------------------------------===//
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def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInFlag]>;
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def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
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//===----------------------------------------------------------------------===//
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// Pseudo Instructions
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//===----------------------------------------------------------------------===//
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def NOP : Pseudo<(outs), (ins), "nop", []>;
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//===----------------------------------------------------------------------===//
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// Real Instructions
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//===----------------------------------------------------------------------===//
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// FIXME: Provide proper encoding!
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let isReturn = 1, isTerminator = 1 in {
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def RETI : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
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}
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//===----------------------------------------------------------------------===//
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// Move Instructions
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// FIXME: Provide proper encoding!
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let neverHasSideEffects = 1 in {
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def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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[]>;
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}
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// FIXME: Provide proper encoding!
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, imm:$src)]>;
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}
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions
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let isTwoAddress = 1 in {
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let Defs = [SR] in {
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let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
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// FIXME: Provide proper encoding!
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def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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let Uses = [SR] in {
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def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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}
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}
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let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
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def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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}
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let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
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def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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}
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def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"sub.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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let Uses = [SR] in {
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def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"subc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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}
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// FIXME: Provide proper encoding!
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def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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"rra.w\t$dst",
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[(set GR16:$dst, (MSP430rra GR16:$src)),
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(implicit SR)]>;
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} // Defs = [SR]
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} // isTwoAddress = 1
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