mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 03:29:40 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22877 91177308-0d34-0410-b5e6-96231b3b80d8
578 lines
22 KiB
C++
578 lines
22 KiB
C++
//===-- PPC32ISelDAGToDAG.cpp - PPC32 pattern matching inst selector ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for 32 bit PowerPC,
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// converting from a legalized dag to a PPC dag.
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//
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//===----------------------------------------------------------------------===//
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#include "PowerPC.h"
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#include "PPC32TargetMachine.h"
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#include "PPC32ISelLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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namespace {
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Statistic<> Recorded("ppc-codegen", "Number of recording ops emitted");
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Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
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Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
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//===--------------------------------------------------------------------===//
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/// PPC32DAGToDAGISel - PPC32 specific code to select PPC32 machine
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/// instructions for SelectionDAG operations.
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///
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class PPC32DAGToDAGISel : public SelectionDAGISel {
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PPC32TargetLowering PPC32Lowering;
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public:
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PPC32DAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDOperand getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDOperand Select(SDOperand Op);
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SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
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unsigned OCHi, unsigned OCLo,
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bool IsArithmetic = false,
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bool Negate = false);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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Select(DAG.getRoot());
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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virtual const char *getPassName() const {
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return "PowerPC DAG->DAG Pattern Instruction Selection";
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}
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};
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}
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// isIntImmediate - This method tests to see if a constant operand.
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// If so Imm will receive the 32 bit value.
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static bool isIntImmediate(SDNode *N, unsigned& Imm) {
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if (N->getOpcode() == ISD::Constant) {
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Imm = cast<ConstantSDNode>(N)->getValue();
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return true;
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}
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return false;
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}
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// isOprShiftImm - Returns true if the specified operand is a shift opcode with
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// a immediate shift count less than 32.
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static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) {
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Opc = N->getOpcode();
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return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
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isIntImmediate(N->getOperand(1).Val, SH) && SH < 32;
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}
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// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
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// any number of 0s on either side. The 1s are allowed to wrap from LSB to
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// MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
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// not, since all 1s are not contiguous.
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static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
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if (isShiftedMask_32(Val)) {
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// look for the first non-zero bit
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MB = CountLeadingZeros_32(Val);
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// look for the first zero bit after the run of ones
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ME = CountLeadingZeros_32((Val - 1) ^ Val);
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return true;
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} else if (isShiftedMask_32(Val = ~Val)) { // invert mask
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// effectively look for the first zero bit
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ME = CountLeadingZeros_32(Val) - 1;
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// effectively look for the first one bit after the run of zeros
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MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
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return true;
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}
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// no run present
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return false;
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}
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// isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate
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// and mask opcode and mask operation.
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static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
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unsigned &SH, unsigned &MB, unsigned &ME) {
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unsigned Shift = 32;
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unsigned Indeterminant = ~0; // bit mask marking indeterminant results
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unsigned Opcode = N->getOpcode();
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if (!isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
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return false;
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if (Opcode == ISD::SHL) {
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// apply shift left to mask if it comes first
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if (IsShiftMask) Mask = Mask << Shift;
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// determine which bits are made indeterminant by shift
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Indeterminant = ~(0xFFFFFFFFu << Shift);
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} else if (Opcode == ISD::SRA || Opcode == ISD::SRL) {
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// apply shift right to mask if it comes first
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if (IsShiftMask) Mask = Mask >> Shift;
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// determine which bits are made indeterminant by shift
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Indeterminant = ~(0xFFFFFFFFu >> Shift);
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// adjust for the left rotate
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Shift = 32 - Shift;
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} else {
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return false;
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}
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// if the mask doesn't intersect any Indeterminant bits
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if (Mask && !(Mask & Indeterminant)) {
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SH = Shift;
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// make sure the mask is still a mask (wrap arounds may not be)
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return isRunOfOnes(Mask, MB, ME);
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}
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return false;
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}
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// isOpcWithIntImmediate - This method tests to see if the node is a specific
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// opcode and that it has a immediate integer right operand.
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// If so Imm will receive the 32 bit value.
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static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
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return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
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}
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// isOprNot - Returns true if the specified operand is an xor with immediate -1.
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static bool isOprNot(SDNode *N) {
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unsigned Imm;
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return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
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}
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// Immediate constant composers.
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// Lo16 - grabs the lo 16 bits from a 32 bit constant.
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// Hi16 - grabs the hi 16 bits from a 32 bit constant.
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// HA16 - computes the hi bits required if the lo bits are add/subtracted in
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// arithmethically.
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static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; }
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static unsigned Hi16(unsigned x) { return Lo16(x >> 16); }
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static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); }
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// isIntImmediate - This method tests to see if a constant operand.
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// If so Imm will receive the 32 bit value.
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static bool isIntImmediate(SDOperand N, unsigned& Imm) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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Imm = (unsigned)CN->getSignExtended();
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return true;
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}
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return false;
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}
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// SelectIntImmediateExpr - Choose code for integer operations with an immediate
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// operand.
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SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
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unsigned OCHi, unsigned OCLo,
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bool IsArithmetic,
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bool Negate) {
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// Check to make sure this is a constant.
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS);
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// Exit if not a constant.
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if (!CN) return 0;
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// Extract immediate.
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unsigned C = (unsigned)CN->getValue();
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// Negate if required (ISD::SUB).
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if (Negate) C = -C;
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// Get the hi and lo portions of constant.
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unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C);
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unsigned Lo = Lo16(C);
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// If two instructions are needed and usage indicates it would be better to
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// load immediate into a register, bail out.
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if (Hi && Lo && CN->use_size() > 2) return false;
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// Select the first operand.
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SDOperand Opr0 = Select(LHS);
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if (Lo) // Add in the lo-part.
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Opr0 = CurDAG->getTargetNode(OCLo, MVT::i32, Opr0, getI32Imm(Lo));
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if (Hi) // Add in the hi-part.
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Opr0 = CurDAG->getTargetNode(OCHi, MVT::i32, Opr0, getI32Imm(Hi));
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return Opr0.Val;
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END)
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return Op; // Already selected.
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switch (N->getOpcode()) {
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default:
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std::cerr << "Cannot yet select: ";
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N->dump();
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std::cerr << "\n";
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abort();
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case ISD::EntryToken: // These leaves remain the same.
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case ISD::UNDEF:
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return Op;
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case ISD::TokenFactor: {
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SDOperand New;
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if (N->getNumOperands() == 2) {
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SDOperand Op0 = Select(N->getOperand(0));
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SDOperand Op1 = Select(N->getOperand(1));
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New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
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} else {
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std::vector<SDOperand> Ops;
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
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Ops.push_back(Select(N->getOperand(0)));
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New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
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}
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if (New.Val != N) {
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CurDAG->ReplaceAllUsesWith(N, New.Val);
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N = New.Val;
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}
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break;
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}
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case ISD::CopyFromReg: {
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SDOperand Chain = Select(N->getOperand(0));
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if (Chain == N->getOperand(0)) return Op; // No change
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SDOperand New = CurDAG->getCopyFromReg(Chain,
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cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
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return New.getValue(Op.ResNo);
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}
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case ISD::CopyToReg: {
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand Reg = N->getOperand(1);
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SDOperand Val = Select(N->getOperand(2));
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if (Chain != N->getOperand(0) || Val != N->getOperand(2)) {
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SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
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Chain, Reg, Val);
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CurDAG->ReplaceAllUsesWith(N, New.Val);
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N = New.Val;
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}
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break;
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}
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case ISD::Constant: {
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assert(N->getValueType(0) == MVT::i32);
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unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
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unsigned Hi = HA16(v);
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unsigned Lo = Lo16(v);
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if (Hi && Lo) {
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SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
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getI32Imm(v >> 16));
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
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} else if (Lo) {
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
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} else {
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::LIS, getI32Imm(v >> 16));
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}
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break;
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}
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case ISD::SIGN_EXTEND_INREG:
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switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
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default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break;
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case MVT::i16:
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSH, Select(N->getOperand(0)));
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break;
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case MVT::i8:
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSB, Select(N->getOperand(0)));
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break;
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}
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break;
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case ISD::CTLZ:
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assert(N->getValueType(0) == MVT::i32);
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::CNTLZW, Select(N->getOperand(0)));
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break;
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case ISD::ADD: {
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MVT::ValueType Ty = N->getValueType(0);
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if (Ty == MVT::i32) {
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if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
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PPC::ADDIS, PPC::ADDI, true)) {
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CurDAG->ReplaceAllUsesWith(N, I);
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N = I;
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} else {
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CurDAG->SelectNodeTo(N, Ty, PPC::ADD, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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}
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break;
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}
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if (!NoExcessFPPrecision) { // Match FMA ops
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if (N->getOperand(0).getOpcode() == ISD::MUL &&
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N->getOperand(0).Val->hasOneUse()) {
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++FusedFP; // Statistic
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CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS,
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Select(N->getOperand(0).getOperand(0)),
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Select(N->getOperand(0).getOperand(1)),
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Select(N->getOperand(1)));
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break;
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} else if (N->getOperand(1).getOpcode() == ISD::MUL &&
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N->getOperand(1).hasOneUse()) {
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++FusedFP; // Statistic
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CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS,
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Select(N->getOperand(1).getOperand(0)),
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Select(N->getOperand(1).getOperand(1)),
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Select(N->getOperand(0)));
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break;
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}
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}
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CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS,
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Select(N->getOperand(0)), Select(N->getOperand(1)));
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break;
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}
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case ISD::SUB: {
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MVT::ValueType Ty = N->getValueType(0);
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if (Ty == MVT::i32) {
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unsigned Imm;
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if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
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CurDAG->SelectNodeTo(N, Ty, PPC::SUBFIC, Select(N->getOperand(1)),
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getI32Imm(Lo16(Imm)));
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break;
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}
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if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
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PPC::ADDIS, PPC::ADDI, true, true)) {
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CurDAG->ReplaceAllUsesWith(N, I);
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N = I;
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} else {
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CurDAG->SelectNodeTo(N, Ty, PPC::SUBF, Select(N->getOperand(1)),
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Select(N->getOperand(0)));
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}
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break;
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}
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if (!NoExcessFPPrecision) { // Match FMA ops
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if (N->getOperand(0).getOpcode() == ISD::MUL &&
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N->getOperand(0).Val->hasOneUse()) {
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++FusedFP; // Statistic
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CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS,
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Select(N->getOperand(0).getOperand(0)),
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Select(N->getOperand(0).getOperand(1)),
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Select(N->getOperand(1)));
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break;
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} else if (N->getOperand(1).getOpcode() == ISD::MUL &&
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N->getOperand(1).Val->hasOneUse()) {
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++FusedFP; // Statistic
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CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS,
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Select(N->getOperand(1).getOperand(0)),
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Select(N->getOperand(1).getOperand(1)),
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Select(N->getOperand(0)));
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break;
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}
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}
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CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS,
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Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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}
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case ISD::MUL: {
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unsigned Imm, Opc;
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if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
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CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULLI,
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Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
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break;
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}
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switch (N->getValueType(0)) {
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default: assert(0 && "Unhandled multiply type!");
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case MVT::i32: Opc = PPC::MULLW; break;
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case MVT::f32: Opc = PPC::FMULS; break;
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case MVT::f64: Opc = PPC::FMUL; break;
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}
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CurDAG->SelectNodeTo(N, N->getValueType(0), Opc, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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}
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case ISD::MULHS:
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assert(N->getValueType(0) == MVT::i32);
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHW, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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case ISD::MULHU:
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assert(N->getValueType(0) == MVT::i32);
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHWU, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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case ISD::AND: {
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unsigned Imm;
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// If this is an and of a value rotated between 0 and 31 bits and then and'd
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// with a mask, emit rlwinm
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if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
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isShiftedMask_32(~Imm))) {
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SDOperand Val;
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unsigned SH, MB, ME;
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if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
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Val = Select(N->getOperand(0).getOperand(0));
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} else {
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Val = Select(N->getOperand(0));
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isRunOfOnes(Imm, MB, ME);
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SH = 0;
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}
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Val, getI32Imm(SH),
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getI32Imm(MB), getI32Imm(ME));
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break;
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}
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// If this is an and with an immediate that isn't a mask, then codegen it as
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// high and low 16 bit immediate ands.
|
|
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
|
|
N->getOperand(1),
|
|
PPC::ANDISo, PPC::ANDIo)) {
|
|
CurDAG->ReplaceAllUsesWith(N, I);
|
|
N = I;
|
|
break;
|
|
}
|
|
// Finally, check for the case where we are being asked to select
|
|
// and (not(a), b) or and (a, not(b)) which can be selected as andc.
|
|
if (isOprNot(N->getOperand(0).Val))
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::ANDC, Select(N->getOperand(1)),
|
|
Select(N->getOperand(0).getOperand(0)));
|
|
else if (isOprNot(N->getOperand(1).Val))
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::ANDC, Select(N->getOperand(0)),
|
|
Select(N->getOperand(1).getOperand(0)));
|
|
else
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::AND, Select(N->getOperand(0)),
|
|
Select(N->getOperand(1)));
|
|
break;
|
|
}
|
|
case ISD::XOR:
|
|
// Check whether or not this node is a logical 'not'. This is represented
|
|
// by llvm as a xor with the constant value -1 (all bits set). If this is a
|
|
// 'not', then fold 'or' into 'nor', and so forth for the supported ops.
|
|
if (isOprNot(N)) {
|
|
unsigned Opc;
|
|
SDOperand Val = Select(N->getOperand(0));
|
|
switch (Val.getTargetOpcode()) {
|
|
default: Opc = 0; break;
|
|
case PPC::OR: Opc = PPC::NOR; break;
|
|
case PPC::AND: Opc = PPC::NAND; break;
|
|
case PPC::XOR: Opc = PPC::EQV; break;
|
|
}
|
|
if (Opc)
|
|
CurDAG->SelectNodeTo(N, MVT::i32, Opc, Val.getOperand(0),
|
|
Val.getOperand(1));
|
|
else
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::NOR, Val, Val);
|
|
break;
|
|
}
|
|
// If this is a xor with an immediate other than -1, then codegen it as high
|
|
// and low 16 bit immediate xors.
|
|
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
|
|
N->getOperand(1),
|
|
PPC::XORIS, PPC::XORI)) {
|
|
CurDAG->ReplaceAllUsesWith(N, I);
|
|
N = I;
|
|
break;
|
|
}
|
|
// Finally, check for the case where we are being asked to select
|
|
// xor (not(a), b) which is equivalent to not(xor a, b), which is eqv
|
|
if (isOprNot(N->getOperand(0).Val))
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::EQV,
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
Select(N->getOperand(1)));
|
|
else
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::XOR, Select(N->getOperand(0)),
|
|
Select(N->getOperand(1)));
|
|
break;
|
|
case ISD::FABS:
|
|
CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::FABS,
|
|
Select(N->getOperand(0)));
|
|
break;
|
|
case ISD::FP_EXTEND:
|
|
assert(MVT::f64 == N->getValueType(0) &&
|
|
MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND");
|
|
CurDAG->SelectNodeTo(N, MVT::f64, PPC::FMR, Select(N->getOperand(0)));
|
|
break;
|
|
case ISD::FP_ROUND:
|
|
assert(MVT::f32 == N->getValueType(0) &&
|
|
MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND");
|
|
CurDAG->SelectNodeTo(N, MVT::f32, PPC::FRSP, Select(N->getOperand(0)));
|
|
break;
|
|
case ISD::FNEG: {
|
|
SDOperand Val = Select(N->getOperand(0));
|
|
MVT::ValueType Ty = N->getValueType(0);
|
|
if (Val.Val->hasOneUse()) {
|
|
unsigned Opc;
|
|
switch (Val.getTargetOpcode()) {
|
|
default: Opc = 0; break;
|
|
case PPC::FABS: Opc = PPC::FNABS; break;
|
|
case PPC::FMADD: Opc = PPC::FNMADD; break;
|
|
case PPC::FMADDS: Opc = PPC::FNMADDS; break;
|
|
case PPC::FMSUB: Opc = PPC::FNMSUB; break;
|
|
case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
|
|
}
|
|
// If we inverted the opcode, then emit the new instruction with the
|
|
// inverted opcode and the original instruction's operands. Otherwise,
|
|
// fall through and generate a fneg instruction.
|
|
if (Opc) {
|
|
if (PPC::FNABS == Opc)
|
|
CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0));
|
|
else
|
|
CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0),
|
|
Val.getOperand(1), Val.getOperand(2));
|
|
break;
|
|
}
|
|
}
|
|
CurDAG->SelectNodeTo(N, Ty, PPC::FNEG, Val);
|
|
break;
|
|
}
|
|
case ISD::FSQRT: {
|
|
MVT::ValueType Ty = N->getValueType(0);
|
|
CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS,
|
|
Select(N->getOperand(0)));
|
|
break;
|
|
}
|
|
case ISD::RET: {
|
|
SDOperand Chain = Select(N->getOperand(0)); // Token chain.
|
|
|
|
if (N->getNumOperands() > 1) {
|
|
SDOperand Val = Select(N->getOperand(1));
|
|
switch (N->getOperand(1).getValueType()) {
|
|
default: assert(0 && "Unknown return type!");
|
|
case MVT::f64:
|
|
case MVT::f32:
|
|
Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
|
|
break;
|
|
case MVT::i32:
|
|
Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
|
|
break;
|
|
}
|
|
|
|
if (N->getNumOperands() > 2) {
|
|
assert(N->getOperand(1).getValueType() == MVT::i32 &&
|
|
N->getOperand(2).getValueType() == MVT::i32 &&
|
|
N->getNumOperands() == 2 && "Unknown two-register ret value!");
|
|
Val = Select(N->getOperand(2));
|
|
Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Val);
|
|
}
|
|
}
|
|
|
|
// Finally, select this to a blr (return) instruction.
|
|
CurDAG->SelectNodeTo(N, MVT::Other, PPC::BLR, Chain);
|
|
break;
|
|
}
|
|
}
|
|
return SDOperand(N, 0);
|
|
}
|
|
|
|
|
|
/// createPPC32ISelDag - This pass converts a legalized DAG into a
|
|
/// PowerPC-specific DAG, ready for instruction scheduling.
|
|
///
|
|
FunctionPass *llvm::createPPC32ISelDag(TargetMachine &TM) {
|
|
return new PPC32DAGToDAGISel(TM);
|
|
}
|
|
|