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or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and PseudoSE (mips32/64 pseudo) classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161071 91177308-0d34-0410-b5e6-96231b3b80d8
258 lines
7.6 KiB
TableGen
258 lines
7.6 KiB
TableGen
//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips16 instructions.
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//
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//===----------------------------------------------------------------------===//
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def uimm5 : Operand<i8> {
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let DecoderMethod= "DecodeSimm16";
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}
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//
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// RRR-type instruction format
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//
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class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
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FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
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//
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// I8_MOV32R instruction format (used only by MOV32R instruction)
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//
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class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
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FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
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!strconcat(asmstr, "\t$r32, $rz"), [], itin>;
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//
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// EXT-RI instruction format
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//
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class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
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!strconcat(asmstr, asmstr2), [], itin>;
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class FEXT_RI16_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
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class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
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FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
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class FEXT_2RI16_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
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!strconcat(asmstr, "\t$rx, $imm"), [], itin> {
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let Constraints = "$rx_ = $rx";
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}
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//
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// RR-type instruction format
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//
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let rx=0 in
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class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
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string asmstr, InstrItinClass itin>:
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FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
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[], itin> ;
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//
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// EXT-RRI instruction format
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//
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class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
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InstrItinClass itin>:
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FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
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!strconcat(asmstr, "\t$ry, $addr"), [], itin>;
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//
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// EXT-SHIFT instruction format
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//
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class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
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FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa),
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!strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
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//
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// Address operand
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def mem16 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops CPU16Regs, simm16);
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let EncoderMethod = "getMemEncoding";
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}
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//
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// Format: ADDIU rx, immediate MIPS16e
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// Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
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// To add a constant to a 32-bit integer.
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//
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class AddiuRxImmX16_base: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
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def AddiuRxImmX16: AddiuRxImmX16_base;
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class AddiuRxRxImmX16_base: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>;
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def AddiuRxRxImmX16: AddiuRxRxImmX16_base;
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//
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// Format: ADDIU rx, pc, immediate MIPS16e
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// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
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// To add a constant to the program counter.
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//
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class AddiuRxPcImmX16_base : FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
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def AddiuRxPcImmX16 : AddiuRxPcImmX16_base;
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//
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// Format: ADDU rz, rx, ry MIPS16e
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// Purpose: Add Unsigned Word (3-Operand)
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// To add 32-bit integers.
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//
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class AdduRxRyRz16_base: FRRR16_ins<01, "addu", IIAlu>;
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def AdduRxRyRz16: AdduRxRyRz16_base;
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//
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// Format: JR ra MIPS16e
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// Purpose: Jump Register Through Register ra
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// To execute a branch to the instruction address in the return
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// address register.
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//
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def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu>;
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//
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// Format: LI rx, immediate MIPS16e
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// Purpose: Load Immediate (Extended)
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// To load a constant into a GPR.
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//
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def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
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//
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// Format: LW ry, offset(rx) MIPS16e
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// Purpose: Load Word (Extended)
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// To load a word from memory as a signed value.
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//
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class LwRxRyOffMemX16_base: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IIAlu>;
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def LwRxRyOffMemX16: LwRxRyOffMemX16_base;
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//
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// Format: MOVE r32, rz MIPS16e
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// Purpose: Move
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// To move the contents of a GPR to a GPR.
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//
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def Mov32R16: FI8_MOV32R16_ins<"move", IIAlu>;
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//
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// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
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// (All args are optional) MIPS16e
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// Purpose: Restore Registers and Deallocate Stack Frame
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// To deallocate a stack frame before exit from a subroutine,
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// restoring return address and static registers, and adjusting
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// stack
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//
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// fixed form for restoring RA and the frame
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// for direct object emitter, encoding needs to be adjusted for the
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// frame size
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//
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let ra=1, s=0,s0=0,s1=0 in
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def RestoreRaF16:
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FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
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"restore \t$$ra, $frame_size", [], IILoad >;
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//
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// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
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// MIPS16e
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// Purpose: Save Registers and Set Up Stack Frame
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// To set up a stack frame on entry to a subroutine,
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// saving return address and static registers, and adjusting stack
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//
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let ra=1, s=1,s0=0,s1=0 in
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def SaveRaF16:
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FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
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"save \t$$ra, $frame_size", [], IILoad >;
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//
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// Format: SLL rx, ry, sa MIPS16e
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// Purpose: Shift Word Left Logical (Extended)
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// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
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//
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def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
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//
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// Format: SW ry, offset(rx) MIPS16e
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// Purpose: Store Word (Extended)
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// To store a word to memory.
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//
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class SwRxRyOffMemX16_base: FEXT_RRI16_mem_ins<0b11011, "sw", mem16, IIAlu>;
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def SwRxRyOffMemX16: SwRxRyOffMemX16_base;
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class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
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let Predicates = [InMips16Mode];
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}
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class ArithLogicR16Defs<SDNode OpNode, bit isComm = 0> {
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dag OutOperandList = (outs CPU16Regs:$rz);
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dag InOperandList = (ins CPU16Regs:$rx, CPU16Regs:$ry);
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list<dag> Pattern = [(set CPU16Regs:$rz,
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(OpNode CPU16Regs:$rx, CPU16Regs:$ry))];
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}
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multiclass ArithLogicR16_base {
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def _add: AdduRxRyRz16_base, ArithLogicR16Defs<add, 1>;
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}
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defm ArithLogicR16_patt : ArithLogicR16_base;
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class LoadM16Defs<PatFrag OpNode, Operand _MemOpnd, bit Pseudo=0> {
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bit isPseudo = Pseudo;
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Operand MemOpnd = _MemOpnd;
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dag OutOperandList = (outs CPU16Regs:$ry);
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dag InOperandList = (ins MemOpnd:$addr);
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list<dag> Pattern = [(set CPU16Regs:$ry, (OpNode addr:$addr))];
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}
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multiclass LoadM16_base {
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def _LwRxRyOffMemX16: LwRxRyOffMemX16_base, LoadM16Defs<load_a, mem16>;
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}
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defm LoadM16: LoadM16_base;
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class StoreM16Defs<PatFrag OpNode, Operand _MemOpnd, bit Pseudo=0> {
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bit isPseudo = Pseudo;
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Operand MemOpnd = _MemOpnd;
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dag OutOperandList = (outs );
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dag InOperandList = (ins CPU16Regs:$ry, MemOpnd:$addr);
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list<dag> Pattern = [(OpNode CPU16Regs:$ry, addr:$addr)];
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}
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multiclass StoreM16_base {
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def _SwRxRyOffMemX16: SwRxRyOffMemX16_base, StoreM16Defs<store_a, mem16>;
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}
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defm StoreM16: StoreM16_base;
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// Jump and Link (Call)
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let isCall=1, hasDelaySlot=1 in
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def JumpLinkReg16:
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FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
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"jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
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// Mips16 pseudos
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let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
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hasExtraSrcRegAllocReq = 1 in
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def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
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// Small immediates
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def : Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
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def : Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
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(AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
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