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https://github.com/c64scene-ar/llvm-6502.git
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0c3682a402
No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203106 91177308-0d34-0410-b5e6-96231b3b80d8
248 lines
8.0 KiB
C++
248 lines
8.0 KiB
C++
//===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Streams SystemZ assembly language and associated data, in the form of
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// MCInsts and MCExprs respectively.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZAsmPrinter.h"
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#include "InstPrinter/SystemZInstPrinter.h"
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#include "SystemZConstantPoolValue.h"
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#include "SystemZMCInstLower.h"
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/IR/Mangler.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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// Return an RI instruction like MI with opcode Opcode, but with the
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// GR64 register operands turned into GR32s.
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static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) {
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if (MI->isCompare())
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
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.addImm(MI->getOperand(1).getImm());
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else
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
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.addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
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.addImm(MI->getOperand(2).getImm());
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}
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// Return an RI instruction like MI with opcode Opcode, but with the
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// GR64 register operands turned into GRH32s.
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static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) {
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if (MI->isCompare())
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
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.addImm(MI->getOperand(1).getImm());
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else
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
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.addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
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.addImm(MI->getOperand(2).getImm());
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}
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// Return an RI instruction like MI with opcode Opcode, but with the
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// R2 register turned into a GR64.
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static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) {
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return MCInstBuilder(Opcode)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
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.addImm(MI->getOperand(3).getImm())
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.addImm(MI->getOperand(4).getImm())
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.addImm(MI->getOperand(5).getImm());
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}
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void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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SystemZMCInstLower Lower(MF->getContext(), *this);
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MCInst LoweredMI;
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switch (MI->getOpcode()) {
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case SystemZ::Return:
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LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D);
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break;
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case SystemZ::CallBRASL:
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LoweredMI = MCInstBuilder(SystemZ::BRASL)
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.addReg(SystemZ::R14D)
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.addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
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break;
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case SystemZ::CallBASR:
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LoweredMI = MCInstBuilder(SystemZ::BASR)
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.addReg(SystemZ::R14D)
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.addReg(MI->getOperand(0).getReg());
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break;
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case SystemZ::CallJG:
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LoweredMI = MCInstBuilder(SystemZ::JG)
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.addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
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break;
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case SystemZ::CallBR:
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LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D);
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break;
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case SystemZ::IILF64:
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LoweredMI = MCInstBuilder(SystemZ::IILF)
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.addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
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.addImm(MI->getOperand(2).getImm());
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break;
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case SystemZ::IIHF64:
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LoweredMI = MCInstBuilder(SystemZ::IIHF)
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.addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
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.addImm(MI->getOperand(2).getImm());
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break;
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case SystemZ::RISBHH:
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case SystemZ::RISBHL:
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LoweredMI = lowerRIEfLow(MI, SystemZ::RISBHG);
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break;
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case SystemZ::RISBLH:
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case SystemZ::RISBLL:
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LoweredMI = lowerRIEfLow(MI, SystemZ::RISBLG);
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break;
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#define LOWER_LOW(NAME) \
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case SystemZ::NAME##64: LoweredMI = lowerRILow(MI, SystemZ::NAME); break
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LOWER_LOW(IILL);
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LOWER_LOW(IILH);
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LOWER_LOW(TMLL);
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LOWER_LOW(TMLH);
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LOWER_LOW(NILL);
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LOWER_LOW(NILH);
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LOWER_LOW(NILF);
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LOWER_LOW(OILL);
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LOWER_LOW(OILH);
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LOWER_LOW(OILF);
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LOWER_LOW(XILF);
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#undef LOWER_LOW
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#define LOWER_HIGH(NAME) \
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case SystemZ::NAME##64: LoweredMI = lowerRIHigh(MI, SystemZ::NAME); break
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LOWER_HIGH(IIHL);
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LOWER_HIGH(IIHH);
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LOWER_HIGH(TMHL);
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LOWER_HIGH(TMHH);
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LOWER_HIGH(NIHL);
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LOWER_HIGH(NIHH);
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LOWER_HIGH(NIHF);
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LOWER_HIGH(OIHL);
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LOWER_HIGH(OIHH);
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LOWER_HIGH(OIHF);
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LOWER_HIGH(XIHF);
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#undef LOWER_HIGH
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case SystemZ::Serialize:
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if (Subtarget->hasFastSerialization())
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LoweredMI = MCInstBuilder(SystemZ::AsmBCR)
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.addImm(14).addReg(SystemZ::R0D);
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else
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LoweredMI = MCInstBuilder(SystemZ::AsmBCR)
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.addImm(15).addReg(SystemZ::R0D);
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break;
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default:
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Lower.lower(MI, LoweredMI);
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break;
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}
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EmitToStreamer(OutStreamer, LoweredMI);
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}
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// Convert a SystemZ-specific constant pool modifier into the associated
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// MCSymbolRefExpr variant kind.
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static MCSymbolRefExpr::VariantKind
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getModifierVariantKind(SystemZCP::SystemZCPModifier Modifier) {
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switch (Modifier) {
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case SystemZCP::NTPOFF: return MCSymbolRefExpr::VK_NTPOFF;
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}
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llvm_unreachable("Invalid SystemCPModifier!");
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}
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void SystemZAsmPrinter::
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EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
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auto *ZCPV = static_cast<SystemZConstantPoolValue*>(MCPV);
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const MCExpr *Expr =
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MCSymbolRefExpr::Create(getSymbol(ZCPV->getGlobalValue()),
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getModifierVariantKind(ZCPV->getModifier()),
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OutContext);
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uint64_t Size = TM.getDataLayout()->getTypeAllocSize(ZCPV->getType());
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OutStreamer.EmitValue(Expr, Size);
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}
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bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI,
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unsigned OpNo,
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unsigned AsmVariant,
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const char *ExtraCode,
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raw_ostream &OS) {
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if (ExtraCode && *ExtraCode == 'n') {
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if (!MI->getOperand(OpNo).isImm())
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return true;
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OS << -int64_t(MI->getOperand(OpNo).getImm());
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} else {
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SystemZMCInstLower Lower(MF->getContext(), *this);
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MCOperand MO(Lower.lowerOperand(MI->getOperand(OpNo)));
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SystemZInstPrinter::printOperand(MO, OS);
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}
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return false;
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}
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bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNo,
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unsigned AsmVariant,
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const char *ExtraCode,
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raw_ostream &OS) {
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SystemZInstPrinter::printAddress(MI->getOperand(OpNo).getReg(),
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MI->getOperand(OpNo + 1).getImm(),
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MI->getOperand(OpNo + 2).getReg(), OS);
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return false;
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}
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void SystemZAsmPrinter::EmitEndOfAsmFile(Module &M) {
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if (Subtarget->isTargetELF()) {
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auto &TLOFELF =
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static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
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MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
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// Output stubs for external and common global variables.
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MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
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if (!Stubs.empty()) {
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OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
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const DataLayout *TD = TM.getDataLayout();
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for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
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OutStreamer.EmitLabel(Stubs[i].first);
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OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(),
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TD->getPointerSize(0));
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}
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Stubs.clear();
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}
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}
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}
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// Force static initialization.
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extern "C" void LLVMInitializeSystemZAsmPrinter() {
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RegisterAsmPrinter<SystemZAsmPrinter> X(TheSystemZTarget);
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}
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