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ebf9f0c6cb
The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204337 91177308-0d34-0410-b5e6-96231b3b80d8
16 lines
391 B
LLVM
16 lines
391 B
LLVM
; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefix=OCTEON
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; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=MIPS64
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define i64 @mul(i64 %a, i64 %b) nounwind {
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entry:
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; OCTEON-LABEL: mul:
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; OCTEON: jr $ra
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; OCTEON: dmul $2, $4, $5
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; MIPS64-LABEL: mul:
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; MIPS64: dmult
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; MIPS64: jr
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; MIPS64: mflo
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%res = mul i64 %a, %b
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ret i64 %res
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}
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