mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ee4fa1977d
CodeGenDAGPatterns, where it can be used in other tablegen backends. This allows the inference to be done for DAGISelEmitter so that it gets accurate mayLoad/mayStore/isSimpleLoad flags. This brings MemOperand functionality back to where it was before 48329. However, it doesn't solve the problem of anonymous patterns which expand to code that does loads or stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49123 91177308-0d34-0410-b5e6-96231b3b80d8
476 lines
17 KiB
C++
476 lines
17 KiB
C++
//===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class wraps target description classes used by the various code
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// generation TableGen backends. This makes it easier to access the data and
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// provides a single place that needs to check it for validity. All of these
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// classes throw exceptions on error conditions.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "CodeGenIntrinsics.h"
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#include "Record.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Streams.h"
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#include <algorithm>
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using namespace llvm;
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static cl::opt<unsigned>
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AsmWriterNum("asmwriternum", cl::init(0),
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cl::desc("Make -gen-asm-writer emit assembly writer #N"));
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/// getValueType - Return the MCV::ValueType that the specified TableGen record
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/// corresponds to.
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MVT::ValueType llvm::getValueType(Record *Rec) {
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return (MVT::ValueType)Rec->getValueAsInt("Value");
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}
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std::string llvm::getName(MVT::ValueType T) {
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switch (T) {
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case MVT::Other: return "UNKNOWN";
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case MVT::i1: return "MVT::i1";
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case MVT::i8: return "MVT::i8";
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case MVT::i16: return "MVT::i16";
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case MVT::i32: return "MVT::i32";
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case MVT::i64: return "MVT::i64";
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case MVT::i128: return "MVT::i128";
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case MVT::iAny: return "MVT::iAny";
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case MVT::fAny: return "MVT::fAny";
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case MVT::f32: return "MVT::f32";
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case MVT::f64: return "MVT::f64";
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case MVT::f80: return "MVT::f80";
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case MVT::f128: return "MVT::f128";
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case MVT::ppcf128: return "MVT::ppcf128";
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case MVT::Flag: return "MVT::Flag";
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case MVT::isVoid:return "MVT::void";
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case MVT::v8i8: return "MVT::v8i8";
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case MVT::v4i16: return "MVT::v4i16";
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case MVT::v2i32: return "MVT::v2i32";
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case MVT::v1i64: return "MVT::v1i64";
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case MVT::v16i8: return "MVT::v16i8";
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case MVT::v8i16: return "MVT::v8i16";
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case MVT::v4i32: return "MVT::v4i32";
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case MVT::v2i64: return "MVT::v2i64";
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case MVT::v2f32: return "MVT::v2f32";
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case MVT::v4f32: return "MVT::v4f32";
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case MVT::v2f64: return "MVT::v2f64";
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case MVT::v3i32: return "MVT::v3i32";
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case MVT::v3f32: return "MVT::v3f32";
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case MVT::iPTR: return "TLI.getPointerTy()";
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default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
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}
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}
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std::string llvm::getEnumName(MVT::ValueType T) {
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switch (T) {
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case MVT::Other: return "MVT::Other";
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case MVT::i1: return "MVT::i1";
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case MVT::i8: return "MVT::i8";
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case MVT::i16: return "MVT::i16";
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case MVT::i32: return "MVT::i32";
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case MVT::i64: return "MVT::i64";
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case MVT::i128: return "MVT::i128";
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case MVT::iAny: return "MVT::iAny";
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case MVT::fAny: return "MVT::fAny";
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case MVT::f32: return "MVT::f32";
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case MVT::f64: return "MVT::f64";
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case MVT::f80: return "MVT::f80";
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case MVT::f128: return "MVT::f128";
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case MVT::ppcf128: return "MVT::ppcf128";
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case MVT::Flag: return "MVT::Flag";
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case MVT::isVoid:return "MVT::isVoid";
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case MVT::v8i8: return "MVT::v8i8";
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case MVT::v4i16: return "MVT::v4i16";
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case MVT::v2i32: return "MVT::v2i32";
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case MVT::v1i64: return "MVT::v1i64";
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case MVT::v16i8: return "MVT::v16i8";
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case MVT::v8i16: return "MVT::v8i16";
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case MVT::v4i32: return "MVT::v4i32";
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case MVT::v2i64: return "MVT::v2i64";
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case MVT::v2f32: return "MVT::v2f32";
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case MVT::v4f32: return "MVT::v4f32";
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case MVT::v2f64: return "MVT::v2f64";
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case MVT::v3i32: return "MVT::v3i32";
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case MVT::v3f32: return "MVT::v3f32";
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case MVT::iPTR: return "MVT::iPTR";
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default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
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}
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}
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/// getQualifiedName - Return the name of the specified record, with a
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/// namespace qualifier if the record contains one.
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///
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std::string llvm::getQualifiedName(const Record *R) {
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std::string Namespace = R->getValueAsString("Namespace");
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if (Namespace.empty()) return R->getName();
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return Namespace + "::" + R->getName();
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}
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/// getTarget - Return the current instance of the Target class.
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///
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CodeGenTarget::CodeGenTarget() {
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std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
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if (Targets.size() == 0)
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throw std::string("ERROR: No 'Target' subclasses defined!");
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if (Targets.size() != 1)
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throw std::string("ERROR: Multiple subclasses of Target defined!");
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TargetRec = Targets[0];
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}
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const std::string &CodeGenTarget::getName() const {
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return TargetRec->getName();
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}
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Record *CodeGenTarget::getInstructionSet() const {
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return TargetRec->getValueAsDef("InstructionSet");
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}
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/// getAsmWriter - Return the AssemblyWriter definition for this target.
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///
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Record *CodeGenTarget::getAsmWriter() const {
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std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
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if (AsmWriterNum >= LI.size())
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throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!";
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return LI[AsmWriterNum];
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}
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void CodeGenTarget::ReadRegisters() const {
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std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
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if (Regs.empty())
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throw std::string("No 'Register' subclasses defined!");
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Registers.reserve(Regs.size());
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Registers.assign(Regs.begin(), Regs.end());
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}
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CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
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DeclaredSpillSize = R->getValueAsInt("SpillSize");
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DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
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}
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const std::string &CodeGenRegister::getName() const {
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return TheDef->getName();
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}
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void CodeGenTarget::ReadRegisterClasses() const {
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std::vector<Record*> RegClasses =
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Records.getAllDerivedDefinitions("RegisterClass");
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if (RegClasses.empty())
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throw std::string("No 'RegisterClass' subclasses defined!");
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RegisterClasses.reserve(RegClasses.size());
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RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
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}
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std::vector<unsigned char> CodeGenTarget::getRegisterVTs(Record *R) const {
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std::vector<unsigned char> Result;
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const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
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for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = RegisterClasses[i];
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for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
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if (R == RC.Elements[ei]) {
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const std::vector<MVT::ValueType> &InVTs = RC.getValueTypes();
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for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
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Result.push_back(InVTs[i]);
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}
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}
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}
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return Result;
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}
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CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
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// Rename anonymous register classes.
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if (R->getName().size() > 9 && R->getName()[9] == '.') {
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static unsigned AnonCounter = 0;
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R->setName("AnonRegClass_"+utostr(AnonCounter++));
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}
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std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
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for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
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Record *Type = TypeList[i];
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if (!Type->isSubClassOf("ValueType"))
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throw "RegTypes list member '" + Type->getName() +
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"' does not derive from the ValueType class!";
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VTs.push_back(getValueType(Type));
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}
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assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
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std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
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for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
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Record *Reg = RegList[i];
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if (!Reg->isSubClassOf("Register"))
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throw "Register Class member '" + Reg->getName() +
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"' does not derive from the Register class!";
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Elements.push_back(Reg);
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}
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std::vector<Record*> SubRegClassList =
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R->getValueAsListOfDefs("SubRegClassList");
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for (unsigned i = 0, e = SubRegClassList.size(); i != e; ++i) {
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Record *SubRegClass = SubRegClassList[i];
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if (!SubRegClass->isSubClassOf("RegisterClass"))
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throw "Register Class member '" + SubRegClass->getName() +
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"' does not derive from the RegisterClass class!";
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SubRegClasses.push_back(SubRegClass);
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}
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// Allow targets to override the size in bits of the RegisterClass.
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unsigned Size = R->getValueAsInt("Size");
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Namespace = R->getValueAsString("Namespace");
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SpillSize = Size ? Size : MVT::getSizeInBits(VTs[0]);
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SpillAlignment = R->getValueAsInt("Alignment");
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CopyCost = R->getValueAsInt("CopyCost");
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MethodBodies = R->getValueAsCode("MethodBodies");
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MethodProtos = R->getValueAsCode("MethodProtos");
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}
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const std::string &CodeGenRegisterClass::getName() const {
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return TheDef->getName();
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}
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void CodeGenTarget::ReadLegalValueTypes() const {
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const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
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for (unsigned i = 0, e = RCs.size(); i != e; ++i)
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for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri)
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LegalValueTypes.push_back(RCs[i].VTs[ri]);
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// Remove duplicates.
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std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
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LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
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LegalValueTypes.end()),
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LegalValueTypes.end());
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}
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void CodeGenTarget::ReadInstructions() const {
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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if (Insts.size() <= 2)
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throw std::string("No 'Instruction' subclasses defined!");
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// Parse the instructions defined in the .td file.
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std::string InstFormatName =
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getAsmWriter()->getValueAsString("InstFormatName");
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for (unsigned i = 0, e = Insts.size(); i != e; ++i) {
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std::string AsmStr = Insts[i]->getValueAsString(InstFormatName);
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Instructions.insert(std::make_pair(Insts[i]->getName(),
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CodeGenInstruction(Insts[i], AsmStr)));
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}
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}
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/// getInstructionsByEnumValue - Return all of the instructions defined by the
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/// target, ordered by their enum value.
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void CodeGenTarget::
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getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
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&NumberedInstructions) {
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std::map<std::string, CodeGenInstruction>::const_iterator I;
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I = getInstructions().find("PHI");
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if (I == Instructions.end()) throw "Could not find 'PHI' instruction!";
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const CodeGenInstruction *PHI = &I->second;
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I = getInstructions().find("INLINEASM");
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if (I == Instructions.end()) throw "Could not find 'INLINEASM' instruction!";
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const CodeGenInstruction *INLINEASM = &I->second;
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I = getInstructions().find("LABEL");
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if (I == Instructions.end()) throw "Could not find 'LABEL' instruction!";
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const CodeGenInstruction *LABEL = &I->second;
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I = getInstructions().find("DECLARE");
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if (I == Instructions.end()) throw "Could not find 'DECLARE' instruction!";
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const CodeGenInstruction *DECLARE = &I->second;
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I = getInstructions().find("EXTRACT_SUBREG");
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if (I == Instructions.end())
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throw "Could not find 'EXTRACT_SUBREG' instruction!";
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const CodeGenInstruction *EXTRACT_SUBREG = &I->second;
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I = getInstructions().find("INSERT_SUBREG");
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if (I == Instructions.end())
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throw "Could not find 'INSERT_SUBREG' instruction!";
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const CodeGenInstruction *INSERT_SUBREG = &I->second;
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I = getInstructions().find("IMPLICIT_DEF");
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if (I == Instructions.end())
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throw "Could not find 'IMPLICIT_DEF' instruction!";
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const CodeGenInstruction *IMPLICIT_DEF = &I->second;
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I = getInstructions().find("SUBREG_TO_REG");
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if (I == Instructions.end())
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throw "Could not find 'SUBREG_TO_REG' instruction!";
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const CodeGenInstruction *SUBREG_TO_REG = &I->second;
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// Print out the rest of the instructions now.
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NumberedInstructions.push_back(PHI);
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NumberedInstructions.push_back(INLINEASM);
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NumberedInstructions.push_back(LABEL);
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NumberedInstructions.push_back(DECLARE);
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NumberedInstructions.push_back(EXTRACT_SUBREG);
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NumberedInstructions.push_back(INSERT_SUBREG);
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NumberedInstructions.push_back(IMPLICIT_DEF);
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NumberedInstructions.push_back(SUBREG_TO_REG);
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for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
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if (&II->second != PHI &&
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&II->second != INLINEASM &&
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&II->second != LABEL &&
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&II->second != DECLARE &&
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&II->second != EXTRACT_SUBREG &&
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&II->second != INSERT_SUBREG &&
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&II->second != IMPLICIT_DEF &&
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&II->second != SUBREG_TO_REG)
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NumberedInstructions.push_back(&II->second);
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}
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/// isLittleEndianEncoding - Return whether this target encodes its instruction
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/// in little-endian format, i.e. bits laid out in the order [0..n]
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///
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bool CodeGenTarget::isLittleEndianEncoding() const {
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return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
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}
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//===----------------------------------------------------------------------===//
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// ComplexPattern implementation
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//
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ComplexPattern::ComplexPattern(Record *R) {
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Ty = ::getValueType(R->getValueAsDef("Ty"));
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NumOperands = R->getValueAsInt("NumOperands");
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SelectFunc = R->getValueAsString("SelectFunc");
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RootNodes = R->getValueAsListOfDefs("RootNodes");
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// Parse the properties.
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Properties = 0;
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std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
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for (unsigned i = 0, e = PropList.size(); i != e; ++i)
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if (PropList[i]->getName() == "SDNPHasChain") {
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Properties |= 1 << SDNPHasChain;
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} else if (PropList[i]->getName() == "SDNPOptInFlag") {
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Properties |= 1 << SDNPOptInFlag;
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} else if (PropList[i]->getName() == "SDNPMayStore") {
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Properties |= 1 << SDNPMayStore;
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} else if (PropList[i]->getName() == "SDNPMayLoad") {
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Properties |= 1 << SDNPMayLoad;
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} else if (PropList[i]->getName() == "SDNPSideEffect") {
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Properties |= 1 << SDNPSideEffect;
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} else {
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cerr << "Unsupported SD Node property '" << PropList[i]->getName()
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<< "' on ComplexPattern '" << R->getName() << "'!\n";
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exit(1);
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}
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// Parse the attributes.
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Attributes = 0;
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PropList = R->getValueAsListOfDefs("Attributes");
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for (unsigned i = 0, e = PropList.size(); i != e; ++i)
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if (PropList[i]->getName() == "CPAttrParentAsRoot") {
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Attributes |= 1 << CPAttrParentAsRoot;
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} else {
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cerr << "Unsupported pattern attribute '" << PropList[i]->getName()
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<< "' on ComplexPattern '" << R->getName() << "'!\n";
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exit(1);
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}
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}
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//===----------------------------------------------------------------------===//
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// CodeGenIntrinsic Implementation
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//===----------------------------------------------------------------------===//
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std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC) {
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std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
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std::vector<CodeGenIntrinsic> Result;
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for (unsigned i = 0, e = I.size(); i != e; ++i)
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Result.push_back(CodeGenIntrinsic(I[i]));
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return Result;
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}
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CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
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TheDef = R;
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std::string DefName = R->getName();
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ModRef = WriteMem;
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isOverloaded = false;
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if (DefName.size() <= 4 ||
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std::string(DefName.begin(), DefName.begin()+4) != "int_")
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throw "Intrinsic '" + DefName + "' does not start with 'int_'!";
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EnumName = std::string(DefName.begin()+4, DefName.end());
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if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
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GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
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TargetPrefix = R->getValueAsString("TargetPrefix");
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Name = R->getValueAsString("LLVMName");
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if (Name == "") {
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// If an explicit name isn't specified, derive one from the DefName.
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Name = "llvm.";
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for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
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if (EnumName[i] == '_')
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Name += '.';
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else
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Name += EnumName[i];
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} else {
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// Verify it starts with "llvm.".
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if (Name.size() <= 5 ||
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std::string(Name.begin(), Name.begin()+5) != "llvm.")
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throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!";
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}
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// If TargetPrefix is specified, make sure that Name starts with
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// "llvm.<targetprefix>.".
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if (!TargetPrefix.empty()) {
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if (Name.size() < 6+TargetPrefix.size() ||
|
|
std::string(Name.begin()+5, Name.begin()+6+TargetPrefix.size())
|
|
!= (TargetPrefix+"."))
|
|
throw "Intrinsic '" + DefName + "' does not start with 'llvm." +
|
|
TargetPrefix + ".'!";
|
|
}
|
|
|
|
// Parse the list of argument types.
|
|
ListInit *TypeList = R->getValueAsListInit("Types");
|
|
for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
|
|
Record *TyEl = TypeList->getElementAsRecord(i);
|
|
assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
|
|
MVT::ValueType VT = getValueType(TyEl->getValueAsDef("VT"));
|
|
isOverloaded |= VT == MVT::iAny || VT == MVT::fAny;
|
|
ArgVTs.push_back(VT);
|
|
ArgTypeDefs.push_back(TyEl);
|
|
}
|
|
if (ArgVTs.size() == 0)
|
|
throw "Intrinsic '"+DefName+"' needs at least a type for the ret value!";
|
|
|
|
|
|
// Parse the intrinsic properties.
|
|
ListInit *PropList = R->getValueAsListInit("Properties");
|
|
for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) {
|
|
Record *Property = PropList->getElementAsRecord(i);
|
|
assert(Property->isSubClassOf("IntrinsicProperty") &&
|
|
"Expected a property!");
|
|
|
|
if (Property->getName() == "IntrNoMem")
|
|
ModRef = NoMem;
|
|
else if (Property->getName() == "IntrReadArgMem")
|
|
ModRef = ReadArgMem;
|
|
else if (Property->getName() == "IntrReadMem")
|
|
ModRef = ReadMem;
|
|
else if (Property->getName() == "IntrWriteArgMem")
|
|
ModRef = WriteArgMem;
|
|
else if (Property->getName() == "IntrWriteMem")
|
|
ModRef = WriteMem;
|
|
else
|
|
assert(0 && "Unknown property!");
|
|
}
|
|
}
|