mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-30 21:29:28 +00:00
Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137404 91177308-0d34-0410-b5e6-96231b3b80d8
1278 lines
46 KiB
C++
1278 lines
46 KiB
C++
//=======- X86FrameLowering.cpp - X86 Frame Information --------*- C++ -*-====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "X86FrameLowering.h"
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#include "X86InstrBuilder.h"
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#include "X86InstrInfo.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86TargetMachine.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/ADT/SmallSet.h"
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using namespace llvm;
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// FIXME: completely move here.
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extern cl::opt<bool> ForceStackAlign;
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// FIXME: Remove once linker support is available. The feature exists only on
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// Darwin at the moment.
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static cl::opt<bool>
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GenerateCompactUnwind("gen-compact-unwind",
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cl::desc("Generate compact unwind encoding"),
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cl::Hidden);
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bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
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return !MF.getFrameInfo()->hasVarSizedObjects();
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}
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/// hasFP - Return true if the specified function should have a dedicated frame
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/// pointer register. This is true if the function has variable sized allocas
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/// or if frame pointer elimination is disabled.
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bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const MachineModuleInfo &MMI = MF.getMMI();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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return (DisableFramePointerElim(MF) ||
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RI->needsStackRealignment(MF) ||
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MFI->hasVarSizedObjects() ||
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MFI->isFrameAddressTaken() ||
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MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
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MMI.callsUnwindInit());
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}
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static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
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if (is64Bit) {
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if (isInt<8>(Imm))
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return X86::SUB64ri8;
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return X86::SUB64ri32;
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} else {
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if (isInt<8>(Imm))
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return X86::SUB32ri8;
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return X86::SUB32ri;
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}
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}
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static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
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if (is64Bit) {
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if (isInt<8>(Imm))
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return X86::ADD64ri8;
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return X86::ADD64ri32;
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} else {
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if (isInt<8>(Imm))
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return X86::ADD32ri8;
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return X86::ADD32ri;
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}
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}
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/// findDeadCallerSavedReg - Return a caller-saved register that isn't live
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/// when it reaches the "return" instruction. We can then pop a stack object
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/// to this register without worry about clobbering it.
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static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const TargetRegisterInfo &TRI,
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bool Is64Bit) {
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const MachineFunction *MF = MBB.getParent();
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const Function *F = MF->getFunction();
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if (!F || MF->getMMI().callsEHReturn())
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return 0;
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static const unsigned CallerSavedRegs32Bit[] = {
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X86::EAX, X86::EDX, X86::ECX, 0
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};
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static const unsigned CallerSavedRegs64Bit[] = {
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X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
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X86::R8, X86::R9, X86::R10, X86::R11, 0
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};
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unsigned Opc = MBBI->getOpcode();
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switch (Opc) {
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default: return 0;
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case X86::RET:
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case X86::RETI:
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case X86::TCRETURNdi:
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case X86::TCRETURNri:
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case X86::TCRETURNmi:
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case X86::TCRETURNdi64:
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case X86::TCRETURNri64:
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case X86::TCRETURNmi64:
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case X86::EH_RETURN:
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case X86::EH_RETURN64: {
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SmallSet<unsigned, 8> Uses;
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for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MBBI->getOperand(i);
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if (!MO.isReg() || MO.isDef())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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for (const unsigned *AsI = TRI.getOverlaps(Reg); *AsI; ++AsI)
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Uses.insert(*AsI);
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}
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const unsigned *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
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for (; *CS; ++CS)
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if (!Uses.count(*CS))
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return *CS;
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}
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}
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return 0;
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}
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/// emitSPUpdate - Emit a series of instructions to increment / decrement the
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/// stack pointer by a constant value.
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static
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void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
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unsigned StackPtr, int64_t NumBytes,
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bool Is64Bit, const TargetInstrInfo &TII,
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const TargetRegisterInfo &TRI) {
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bool isSub = NumBytes < 0;
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uint64_t Offset = isSub ? -NumBytes : NumBytes;
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unsigned Opc = isSub ?
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getSUBriOpcode(Is64Bit, Offset) :
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getADDriOpcode(Is64Bit, Offset);
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uint64_t Chunk = (1LL << 31) - 1;
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DebugLoc DL = MBB.findDebugLoc(MBBI);
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while (Offset) {
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uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
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if (ThisVal == (Is64Bit ? 8 : 4)) {
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// Use push / pop instead.
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unsigned Reg = isSub
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? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
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: findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
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if (Reg) {
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Opc = isSub
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? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
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: (Is64Bit ? X86::POP64r : X86::POP32r);
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MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
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.addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
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if (isSub)
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MI->setFlag(MachineInstr::FrameSetup);
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Offset -= ThisVal;
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continue;
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}
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}
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
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.addReg(StackPtr)
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.addImm(ThisVal);
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if (isSub)
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MI->setFlag(MachineInstr::FrameSetup);
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MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
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Offset -= ThisVal;
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}
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}
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/// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
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static
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void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
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unsigned StackPtr, uint64_t *NumBytes = NULL) {
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if (MBBI == MBB.begin()) return;
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MachineBasicBlock::iterator PI = prior(MBBI);
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unsigned Opc = PI->getOpcode();
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if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
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Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
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PI->getOperand(0).getReg() == StackPtr) {
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if (NumBytes)
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*NumBytes += PI->getOperand(2).getImm();
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MBB.erase(PI);
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} else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
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Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
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PI->getOperand(0).getReg() == StackPtr) {
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if (NumBytes)
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*NumBytes -= PI->getOperand(2).getImm();
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MBB.erase(PI);
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}
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}
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/// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator.
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static
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void mergeSPUpdatesDown(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned StackPtr, uint64_t *NumBytes = NULL) {
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// FIXME: THIS ISN'T RUN!!!
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return;
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if (MBBI == MBB.end()) return;
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MachineBasicBlock::iterator NI = llvm::next(MBBI);
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if (NI == MBB.end()) return;
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unsigned Opc = NI->getOpcode();
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if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
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Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
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NI->getOperand(0).getReg() == StackPtr) {
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if (NumBytes)
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*NumBytes -= NI->getOperand(2).getImm();
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MBB.erase(NI);
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MBBI = NI;
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} else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
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Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
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NI->getOperand(0).getReg() == StackPtr) {
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if (NumBytes)
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*NumBytes += NI->getOperand(2).getImm();
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MBB.erase(NI);
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MBBI = NI;
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}
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}
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/// mergeSPUpdates - Checks the instruction before/after the passed
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/// instruction. If it is an ADD/SUB instruction it is deleted argument and the
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/// stack adjustment is returned as a positive value for ADD and a negative for
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/// SUB.
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static int mergeSPUpdates(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned StackPtr,
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bool doMergeWithPrevious) {
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if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
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(!doMergeWithPrevious && MBBI == MBB.end()))
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return 0;
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MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
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MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
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unsigned Opc = PI->getOpcode();
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int Offset = 0;
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if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
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Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
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PI->getOperand(0).getReg() == StackPtr){
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Offset += PI->getOperand(2).getImm();
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MBB.erase(PI);
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if (!doMergeWithPrevious) MBBI = NI;
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} else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
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Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
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PI->getOperand(0).getReg() == StackPtr) {
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Offset -= PI->getOperand(2).getImm();
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MBB.erase(PI);
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if (!doMergeWithPrevious) MBBI = NI;
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}
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return Offset;
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}
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static bool isEAXLiveIn(MachineFunction &MF) {
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for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
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EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
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unsigned Reg = II->first;
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if (Reg == X86::EAX || Reg == X86::AX ||
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Reg == X86::AH || Reg == X86::AL)
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return true;
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}
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return false;
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}
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void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
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MCSymbol *Label,
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unsigned FramePtr) const {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineModuleInfo &MMI = MF.getMMI();
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// Add callee saved registers to move list.
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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if (CSI.empty()) return;
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std::vector<MachineMove> &Moves = MMI.getFrameMoves();
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const TargetData *TD = TM.getTargetData();
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bool HasFP = hasFP(MF);
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// Calculate amount of bytes used for return address storing.
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int stackGrowth = -TD->getPointerSize();
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// FIXME: This is dirty hack. The code itself is pretty mess right now.
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// It should be rewritten from scratch and generalized sometimes.
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// Determine maximum offset (minimum due to stack growth).
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int64_t MaxOffset = 0;
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for (std::vector<CalleeSavedInfo>::const_iterator
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I = CSI.begin(), E = CSI.end(); I != E; ++I)
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MaxOffset = std::min(MaxOffset,
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MFI->getObjectOffset(I->getFrameIdx()));
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// Calculate offsets.
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int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
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for (std::vector<CalleeSavedInfo>::const_iterator
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I = CSI.begin(), E = CSI.end(); I != E; ++I) {
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int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
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unsigned Reg = I->getReg();
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Offset = MaxOffset - Offset + saveAreaOffset;
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// Don't output a new machine move if we're re-saving the frame
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// pointer. This happens when the PrologEpilogInserter has inserted an extra
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// "PUSH" of the frame pointer -- the "emitPrologue" method automatically
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// generates one when frame pointers are used. If we generate a "machine
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// move" for this extra "PUSH", the linker will lose track of the fact that
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// the frame pointer should have the value of the first "PUSH" when it's
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// trying to unwind.
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//
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// FIXME: This looks inelegant. It's possibly correct, but it's covering up
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// another bug. I.e., one where we generate a prolog like this:
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//
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// pushl %ebp
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// movl %esp, %ebp
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// pushl %ebp
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// pushl %esi
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// ...
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//
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// The immediate re-push of EBP is unnecessary. At the least, it's an
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// optimization bug. EBP can be used as a scratch register in certain
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// cases, but probably not when we have a frame pointer.
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if (HasFP && FramePtr == Reg)
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continue;
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MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
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MachineLocation CSSrc(Reg);
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Moves.push_back(MachineMove(Label, CSDst, CSSrc));
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}
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}
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/// getCompactUnwindRegNum - Get the compact unwind number for a given
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/// register. The number corresponds to the enum lists in
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/// compact_unwind_encoding.h.
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static int getCompactUnwindRegNum(const unsigned *CURegs, unsigned Reg) {
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int Idx = 1;
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for (; *CURegs; ++CURegs, ++Idx)
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if (*CURegs == Reg)
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return Idx;
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return -1;
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}
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/// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding
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/// used with frameless stacks. It is passed the number of registers to be saved
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/// and an array of the registers saved.
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static uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[6],
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unsigned RegCount,
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bool Is64Bit) {
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// The saved registers are numbered from 1 to 6. In order to encode the order
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// in which they were saved, we re-number them according to their place in the
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// register order. The re-numbering is relative to the last re-numbered
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// register. E.g., if we have registers {6, 2, 4, 5} saved in that order:
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//
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// Orig Re-Num
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// ---- ------
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// 6 6
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// 2 2
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// 4 3
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// 5 3
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//
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static const unsigned CU32BitRegs[] = {
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X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
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};
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static const unsigned CU64BitRegs[] = {
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X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
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};
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const unsigned *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
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uint32_t RenumRegs[6];
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for (unsigned i = 6 - RegCount; i < 6; ++i) {
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int CUReg = getCompactUnwindRegNum(CURegs, SavedRegs[i]);
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if (CUReg == -1) return ~0U;
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SavedRegs[i] = CUReg;
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unsigned Countless = 0;
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for (unsigned j = 6 - RegCount; j < i; ++j)
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if (SavedRegs[j] < SavedRegs[i])
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++Countless;
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RenumRegs[i] = SavedRegs[i] - Countless - 1;
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}
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// Take the renumbered values and encode them into a 10-bit number.
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uint32_t permutationEncoding = 0;
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switch (RegCount) {
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case 6:
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permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
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+ 6 * RenumRegs[2] + 2 * RenumRegs[3]
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+ RenumRegs[4];
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break;
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case 5:
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permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
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+ 6 * RenumRegs[3] + 2 * RenumRegs[4]
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+ RenumRegs[5];
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break;
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case 4:
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permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
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+ 3 * RenumRegs[4] + RenumRegs[5];
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break;
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case 3:
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permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
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+ RenumRegs[5];
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break;
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case 2:
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permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
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break;
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case 1:
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permutationEncoding |= RenumRegs[5];
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break;
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}
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assert((permutationEncoding & 0x3FF) == permutationEncoding &&
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"Invalid compact register encoding!");
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return permutationEncoding;
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}
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/// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a
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/// compact encoding with a frame pointer.
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static uint32_t encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[6],
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bool Is64Bit) {
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static const unsigned CU32BitRegs[] = {
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X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
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};
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static const unsigned CU64BitRegs[] = {
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X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
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};
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const unsigned *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
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// Encode the registers in the order they were saved, 3-bits per register. The
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// registers are numbered from 1 to 6.
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|
uint32_t RegEnc = 0;
|
|
for (int I = 5; I >= 0; --I) {
|
|
unsigned Reg = SavedRegs[I];
|
|
if (Reg == 0) break;
|
|
int CURegNum = getCompactUnwindRegNum(CURegs, Reg);
|
|
if (CURegNum == -1)
|
|
return ~0U;
|
|
RegEnc |= (CURegNum & 0x7) << (5 - I);
|
|
}
|
|
|
|
assert((RegEnc & 0x7FFF) == RegEnc && "Invalid compact register encoding!");
|
|
return RegEnc;
|
|
}
|
|
|
|
uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const {
|
|
const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
|
|
unsigned FramePtr = RegInfo->getFrameRegister(MF);
|
|
unsigned StackPtr = RegInfo->getStackRegister();
|
|
|
|
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
|
|
int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
|
|
|
|
bool Is64Bit = STI.is64Bit();
|
|
bool HasFP = hasFP(MF);
|
|
|
|
unsigned SavedRegs[6] = { 0, 0, 0, 0, 0, 0 };
|
|
int SavedRegIdx = 6;
|
|
|
|
unsigned OffsetSize = (Is64Bit ? 8 : 4);
|
|
|
|
unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
|
|
unsigned PushInstrSize = 1;
|
|
unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
|
|
unsigned MoveInstrSize = (Is64Bit ? 3 : 2);
|
|
unsigned SubtractInstr = getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta);
|
|
unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2);
|
|
|
|
unsigned StackDivide = (Is64Bit ? 8 : 4);
|
|
|
|
unsigned InstrOffset = 0;
|
|
unsigned CFAOffset = 0;
|
|
unsigned StackAdjust = 0;
|
|
|
|
MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB.
|
|
bool ExpectEnd = false;
|
|
for (MachineBasicBlock::iterator
|
|
MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) {
|
|
MachineInstr &MI = *MBBI;
|
|
unsigned Opc = MI.getOpcode();
|
|
if (Opc == X86::PROLOG_LABEL) continue;
|
|
if (!MI.getFlag(MachineInstr::FrameSetup)) break;
|
|
|
|
// We don't exect any more prolog instructions.
|
|
if (ExpectEnd) return 0;
|
|
|
|
if (Opc == PushInstr) {
|
|
// If there are too many saved registers, we cannot use compact encoding.
|
|
if (--SavedRegIdx < 0) return 0;
|
|
|
|
SavedRegs[SavedRegIdx] = MI.getOperand(0).getReg();
|
|
CFAOffset += OffsetSize;
|
|
InstrOffset += PushInstrSize;
|
|
} else if (Opc == MoveInstr) {
|
|
unsigned SrcReg = MI.getOperand(1).getReg();
|
|
unsigned DstReg = MI.getOperand(0).getReg();
|
|
|
|
if (DstReg != FramePtr || SrcReg != StackPtr)
|
|
return 0;
|
|
|
|
CFAOffset = 0;
|
|
memset(SavedRegs, 0, sizeof(SavedRegs));
|
|
InstrOffset += MoveInstrSize;
|
|
} else if (Opc == SubtractInstr) {
|
|
if (StackAdjust)
|
|
// We all ready have a stack pointer adjustment.
|
|
return 0;
|
|
|
|
if (!MI.getOperand(0).isReg() ||
|
|
MI.getOperand(0).getReg() != MI.getOperand(1).getReg() ||
|
|
MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm())
|
|
// We need this to be a stack adjustment pointer. Something like:
|
|
//
|
|
// %RSP<def> = SUB64ri8 %RSP, 48
|
|
return 0;
|
|
|
|
StackAdjust = MI.getOperand(2).getImm() / StackDivide;
|
|
SubtractInstrIdx += InstrOffset;
|
|
ExpectEnd = true;
|
|
}
|
|
}
|
|
|
|
// Encode that we are using EBP/RBP as the frame pointer.
|
|
uint32_t CompactUnwindEncoding = 0;
|
|
CFAOffset /= StackDivide;
|
|
if (HasFP) {
|
|
if ((CFAOffset & 0xFF) != CFAOffset)
|
|
// Offset was too big for compact encoding.
|
|
return 0;
|
|
|
|
// Get the encoding of the saved registers when we have a frame pointer.
|
|
uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit);
|
|
if (RegEnc == ~0U)
|
|
return 0;
|
|
|
|
CompactUnwindEncoding |= 0x01000000;
|
|
CompactUnwindEncoding |= (CFAOffset & 0xFF) << 16;
|
|
CompactUnwindEncoding |= RegEnc & 0x7FFF;
|
|
} else {
|
|
unsigned FullOffset = CFAOffset + StackAdjust;
|
|
if ((FullOffset & 0xFF) == FullOffset) {
|
|
// Frameless stack.
|
|
CompactUnwindEncoding |= 0x02000000;
|
|
CompactUnwindEncoding |= (FullOffset & 0xFF) << 16;
|
|
} else {
|
|
if ((CFAOffset & 0x7) != CFAOffset)
|
|
// The extra stack adjustments are too big for us to handle.
|
|
return 0;
|
|
|
|
// Frameless stack with an offset too large for us to encode compactly.
|
|
CompactUnwindEncoding |= 0x03000000;
|
|
|
|
// Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
|
|
// instruction.
|
|
CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
|
|
|
|
// Encode any extra stack stack changes (done via push instructions).
|
|
CompactUnwindEncoding |= (CFAOffset & 0x7) << 13;
|
|
}
|
|
|
|
// Get the encoding of the saved registers when we don't have a frame
|
|
// pointer.
|
|
uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegs,
|
|
6 - SavedRegIdx,
|
|
Is64Bit);
|
|
if (RegEnc == ~0U) return 0;
|
|
CompactUnwindEncoding |= RegEnc & 0x3FF;
|
|
}
|
|
|
|
return CompactUnwindEncoding;
|
|
}
|
|
|
|
/// emitPrologue - Push callee-saved registers onto the stack, which
|
|
/// automatically adjust the stack pointer. Adjust the stack pointer to allocate
|
|
/// space for local variables. Also emit labels used by the exception handler to
|
|
/// generate the exception handling frames.
|
|
void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
|
|
MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
|
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const Function *Fn = MF.getFunction();
|
|
const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
|
|
const X86InstrInfo &TII = *TM.getInstrInfo();
|
|
MachineModuleInfo &MMI = MF.getMMI();
|
|
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
|
|
bool needsFrameMoves = MMI.hasDebugInfo() ||
|
|
Fn->needsUnwindTableEntry();
|
|
uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
|
|
uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
|
|
bool HasFP = hasFP(MF);
|
|
bool Is64Bit = STI.is64Bit();
|
|
bool IsWin64 = STI.isTargetWin64();
|
|
unsigned StackAlign = getStackAlignment();
|
|
unsigned SlotSize = RegInfo->getSlotSize();
|
|
unsigned FramePtr = RegInfo->getFrameRegister(MF);
|
|
unsigned StackPtr = RegInfo->getStackRegister();
|
|
DebugLoc DL;
|
|
|
|
// If we're forcing a stack realignment we can't rely on just the frame
|
|
// info, we need to know the ABI stack alignment as well in case we
|
|
// have a call out. Otherwise just make sure we have some alignment - we'll
|
|
// go with the minimum SlotSize.
|
|
if (ForceStackAlign) {
|
|
if (MFI->hasCalls())
|
|
MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
|
|
else if (MaxAlign < SlotSize)
|
|
MaxAlign = SlotSize;
|
|
}
|
|
|
|
// Add RETADDR move area to callee saved frame size.
|
|
int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
|
|
if (TailCallReturnAddrDelta < 0)
|
|
X86FI->setCalleeSavedFrameSize(
|
|
X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
|
|
|
|
// If this is x86-64 and the Red Zone is not disabled, if we are a leaf
|
|
// function, and use up to 128 bytes of stack space, don't have a frame
|
|
// pointer, calls, or dynamic alloca then we do not need to adjust the
|
|
// stack pointer (we fit in the Red Zone).
|
|
if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
|
|
!RegInfo->needsStackRealignment(MF) &&
|
|
!MFI->hasVarSizedObjects() && // No dynamic alloca.
|
|
!MFI->adjustsStack() && // No calls.
|
|
!IsWin64) { // Win64 has no Red Zone
|
|
uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
|
|
if (HasFP) MinSize += SlotSize;
|
|
StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
|
|
MFI->setStackSize(StackSize);
|
|
}
|
|
|
|
// Insert stack pointer adjustment for later moving of return addr. Only
|
|
// applies to tail call optimized functions where the callee argument stack
|
|
// size is bigger than the callers.
|
|
if (TailCallReturnAddrDelta < 0) {
|
|
MachineInstr *MI =
|
|
BuildMI(MBB, MBBI, DL,
|
|
TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
|
|
StackPtr)
|
|
.addReg(StackPtr)
|
|
.addImm(-TailCallReturnAddrDelta)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
|
|
}
|
|
|
|
// Mapping for machine moves:
|
|
//
|
|
// DST: VirtualFP AND
|
|
// SRC: VirtualFP => DW_CFA_def_cfa_offset
|
|
// ELSE => DW_CFA_def_cfa
|
|
//
|
|
// SRC: VirtualFP AND
|
|
// DST: Register => DW_CFA_def_cfa_register
|
|
//
|
|
// ELSE
|
|
// OFFSET < 0 => DW_CFA_offset_extended_sf
|
|
// REG < 64 => DW_CFA_offset + Reg
|
|
// ELSE => DW_CFA_offset_extended
|
|
|
|
std::vector<MachineMove> &Moves = MMI.getFrameMoves();
|
|
const TargetData *TD = MF.getTarget().getTargetData();
|
|
uint64_t NumBytes = 0;
|
|
int stackGrowth = -TD->getPointerSize();
|
|
|
|
if (HasFP) {
|
|
// Calculate required stack adjustment.
|
|
uint64_t FrameSize = StackSize - SlotSize;
|
|
if (RegInfo->needsStackRealignment(MF))
|
|
FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
|
|
|
|
NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
|
|
|
|
// Get the offset of the stack slot for the EBP register, which is
|
|
// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
|
|
// Update the frame offset adjustment.
|
|
MFI->setOffsetAdjustment(-NumBytes);
|
|
|
|
// Save EBP/RBP into the appropriate stack slot.
|
|
BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
|
|
.addReg(FramePtr, RegState::Kill)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
if (needsFrameMoves) {
|
|
// Mark the place where EBP/RBP was saved.
|
|
MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
|
|
BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
|
|
.addSym(FrameLabel);
|
|
|
|
// Define the current CFA rule to use the provided offset.
|
|
if (StackSize) {
|
|
MachineLocation SPDst(MachineLocation::VirtualFP);
|
|
MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
|
|
Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
|
|
} else {
|
|
MachineLocation SPDst(StackPtr);
|
|
MachineLocation SPSrc(StackPtr, stackGrowth);
|
|
Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
|
|
}
|
|
|
|
// Change the rule for the FramePtr to be an "offset" rule.
|
|
MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
|
|
MachineLocation FPSrc(FramePtr);
|
|
Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
|
|
}
|
|
|
|
// Update EBP with the new base value.
|
|
BuildMI(MBB, MBBI, DL,
|
|
TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
|
|
.addReg(StackPtr)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
if (needsFrameMoves) {
|
|
// Mark effective beginning of when frame pointer becomes valid.
|
|
MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
|
|
BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
|
|
.addSym(FrameLabel);
|
|
|
|
// Define the current CFA to use the EBP/RBP register.
|
|
MachineLocation FPDst(FramePtr);
|
|
MachineLocation FPSrc(MachineLocation::VirtualFP);
|
|
Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
|
|
}
|
|
|
|
// Mark the FramePtr as live-in in every block except the entry.
|
|
for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
|
|
I != E; ++I)
|
|
I->addLiveIn(FramePtr);
|
|
|
|
// Realign stack
|
|
if (RegInfo->needsStackRealignment(MF)) {
|
|
MachineInstr *MI =
|
|
BuildMI(MBB, MBBI, DL,
|
|
TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
|
|
.addReg(StackPtr)
|
|
.addImm(-MaxAlign)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
// The EFLAGS implicit def is dead.
|
|
MI->getOperand(3).setIsDead();
|
|
}
|
|
} else {
|
|
NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
|
|
}
|
|
|
|
// Skip the callee-saved push instructions.
|
|
bool PushedRegs = false;
|
|
int StackOffset = 2 * stackGrowth;
|
|
|
|
while (MBBI != MBB.end() &&
|
|
(MBBI->getOpcode() == X86::PUSH32r ||
|
|
MBBI->getOpcode() == X86::PUSH64r)) {
|
|
PushedRegs = true;
|
|
MBBI->setFlag(MachineInstr::FrameSetup);
|
|
++MBBI;
|
|
|
|
if (!HasFP && needsFrameMoves) {
|
|
// Mark callee-saved push instruction.
|
|
MCSymbol *Label = MMI.getContext().CreateTempSymbol();
|
|
BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
|
|
|
|
// Define the current CFA rule to use the provided offset.
|
|
unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr;
|
|
MachineLocation SPDst(Ptr);
|
|
MachineLocation SPSrc(Ptr, StackOffset);
|
|
Moves.push_back(MachineMove(Label, SPDst, SPSrc));
|
|
StackOffset += stackGrowth;
|
|
}
|
|
}
|
|
|
|
DL = MBB.findDebugLoc(MBBI);
|
|
|
|
// If there is an SUB32ri of ESP immediately before this instruction, merge
|
|
// the two. This can be the case when tail call elimination is enabled and
|
|
// the callee has more arguments then the caller.
|
|
NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
|
|
|
|
// If there is an ADD32ri or SUB32ri of ESP immediately after this
|
|
// instruction, merge the two instructions.
|
|
mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
|
|
|
|
// Adjust stack pointer: ESP -= numbytes.
|
|
|
|
// Windows and cygwin/mingw require a prologue helper routine when allocating
|
|
// more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
|
|
// uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
|
|
// stack and adjust the stack pointer in one go. The 64-bit version of
|
|
// __chkstk is only responsible for probing the stack. The 64-bit prologue is
|
|
// responsible for adjusting the stack pointer. Touching the stack at 4K
|
|
// increments is necessary to ensure that the guard pages used by the OS
|
|
// virtual memory manager are allocated in correct sequence.
|
|
if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) {
|
|
const char *StackProbeSymbol;
|
|
bool isSPUpdateNeeded = false;
|
|
|
|
if (Is64Bit) {
|
|
if (STI.isTargetCygMing())
|
|
StackProbeSymbol = "___chkstk";
|
|
else {
|
|
StackProbeSymbol = "__chkstk";
|
|
isSPUpdateNeeded = true;
|
|
}
|
|
} else if (STI.isTargetCygMing())
|
|
StackProbeSymbol = "_alloca";
|
|
else
|
|
StackProbeSymbol = "_chkstk";
|
|
|
|
// Check whether EAX is livein for this function.
|
|
bool isEAXAlive = isEAXLiveIn(MF);
|
|
|
|
if (isEAXAlive) {
|
|
// Sanity check that EAX is not livein for this function.
|
|
// It should not be, so throw an assert.
|
|
assert(!Is64Bit && "EAX is livein in x64 case!");
|
|
|
|
// Save EAX
|
|
BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
|
|
.addReg(X86::EAX, RegState::Kill)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
}
|
|
|
|
if (Is64Bit) {
|
|
// Handle the 64-bit Windows ABI case where we need to call __chkstk.
|
|
// Function prologue is responsible for adjusting the stack pointer.
|
|
BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
|
|
.addImm(NumBytes)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
} else {
|
|
// Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
|
|
// We'll also use 4 already allocated bytes for EAX.
|
|
BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
|
|
.addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
}
|
|
|
|
BuildMI(MBB, MBBI, DL,
|
|
TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
|
|
.addExternalSymbol(StackProbeSymbol)
|
|
.addReg(StackPtr, RegState::Define | RegState::Implicit)
|
|
.addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
// MSVC x64's __chkstk needs to adjust %rsp.
|
|
// FIXME: %rax preserves the offset and should be available.
|
|
if (isSPUpdateNeeded)
|
|
emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
|
|
TII, *RegInfo);
|
|
|
|
if (isEAXAlive) {
|
|
// Restore EAX
|
|
MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
|
|
X86::EAX),
|
|
StackPtr, false, NumBytes - 4);
|
|
MI->setFlag(MachineInstr::FrameSetup);
|
|
MBB.insert(MBBI, MI);
|
|
}
|
|
} else if (NumBytes)
|
|
emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
|
|
TII, *RegInfo);
|
|
|
|
if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
|
|
// Mark end of stack pointer adjustment.
|
|
MCSymbol *Label = MMI.getContext().CreateTempSymbol();
|
|
BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
|
|
.addSym(Label);
|
|
|
|
if (!HasFP && NumBytes) {
|
|
// Define the current CFA rule to use the provided offset.
|
|
if (StackSize) {
|
|
MachineLocation SPDst(MachineLocation::VirtualFP);
|
|
MachineLocation SPSrc(MachineLocation::VirtualFP,
|
|
-StackSize + stackGrowth);
|
|
Moves.push_back(MachineMove(Label, SPDst, SPSrc));
|
|
} else {
|
|
MachineLocation SPDst(StackPtr);
|
|
MachineLocation SPSrc(StackPtr, stackGrowth);
|
|
Moves.push_back(MachineMove(Label, SPDst, SPSrc));
|
|
}
|
|
}
|
|
|
|
// Emit DWARF info specifying the offsets of the callee-saved registers.
|
|
if (PushedRegs)
|
|
emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
|
|
}
|
|
|
|
// Darwin 10.7 and greater has support for compact unwind encoding.
|
|
if (GenerateCompactUnwind &&
|
|
STI.isTargetDarwin() && !STI.getTargetTriple().isMacOSXVersionLT(10, 6))
|
|
MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF));
|
|
}
|
|
|
|
void X86FrameLowering::emitEpilogue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
|
|
const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
|
|
const X86InstrInfo &TII = *TM.getInstrInfo();
|
|
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
|
|
assert(MBBI != MBB.end() && "Returning block has no instructions");
|
|
unsigned RetOpcode = MBBI->getOpcode();
|
|
DebugLoc DL = MBBI->getDebugLoc();
|
|
bool Is64Bit = STI.is64Bit();
|
|
unsigned StackAlign = getStackAlignment();
|
|
unsigned SlotSize = RegInfo->getSlotSize();
|
|
unsigned FramePtr = RegInfo->getFrameRegister(MF);
|
|
unsigned StackPtr = RegInfo->getStackRegister();
|
|
|
|
switch (RetOpcode) {
|
|
default:
|
|
llvm_unreachable("Can only insert epilog into returning blocks");
|
|
case X86::RET:
|
|
case X86::RETI:
|
|
case X86::TCRETURNdi:
|
|
case X86::TCRETURNri:
|
|
case X86::TCRETURNmi:
|
|
case X86::TCRETURNdi64:
|
|
case X86::TCRETURNri64:
|
|
case X86::TCRETURNmi64:
|
|
case X86::EH_RETURN:
|
|
case X86::EH_RETURN64:
|
|
break; // These are ok
|
|
}
|
|
|
|
// Get the number of bytes to allocate from the FrameInfo.
|
|
uint64_t StackSize = MFI->getStackSize();
|
|
uint64_t MaxAlign = MFI->getMaxAlignment();
|
|
unsigned CSSize = X86FI->getCalleeSavedFrameSize();
|
|
uint64_t NumBytes = 0;
|
|
|
|
// If we're forcing a stack realignment we can't rely on just the frame
|
|
// info, we need to know the ABI stack alignment as well in case we
|
|
// have a call out. Otherwise just make sure we have some alignment - we'll
|
|
// go with the minimum.
|
|
if (ForceStackAlign) {
|
|
if (MFI->hasCalls())
|
|
MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
|
|
else
|
|
MaxAlign = MaxAlign ? MaxAlign : 4;
|
|
}
|
|
|
|
if (hasFP(MF)) {
|
|
// Calculate required stack adjustment.
|
|
uint64_t FrameSize = StackSize - SlotSize;
|
|
if (RegInfo->needsStackRealignment(MF))
|
|
FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
|
|
|
|
NumBytes = FrameSize - CSSize;
|
|
|
|
// Pop EBP.
|
|
BuildMI(MBB, MBBI, DL,
|
|
TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
|
|
} else {
|
|
NumBytes = StackSize - CSSize;
|
|
}
|
|
|
|
// Skip the callee-saved pop instructions.
|
|
MachineBasicBlock::iterator LastCSPop = MBBI;
|
|
while (MBBI != MBB.begin()) {
|
|
MachineBasicBlock::iterator PI = prior(MBBI);
|
|
unsigned Opc = PI->getOpcode();
|
|
|
|
if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
|
|
!PI->getDesc().isTerminator())
|
|
break;
|
|
|
|
--MBBI;
|
|
}
|
|
|
|
DL = MBBI->getDebugLoc();
|
|
|
|
// If there is an ADD32ri or SUB32ri of ESP immediately before this
|
|
// instruction, merge the two instructions.
|
|
if (NumBytes || MFI->hasVarSizedObjects())
|
|
mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
|
|
|
|
// If dynamic alloca is used, then reset esp to point to the last callee-saved
|
|
// slot before popping them off! Same applies for the case, when stack was
|
|
// realigned.
|
|
if (RegInfo->needsStackRealignment(MF)) {
|
|
// We cannot use LEA here, because stack pointer was realigned. We need to
|
|
// deallocate local frame back.
|
|
if (CSSize) {
|
|
emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII, *RegInfo);
|
|
MBBI = prior(LastCSPop);
|
|
}
|
|
|
|
BuildMI(MBB, MBBI, DL,
|
|
TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
|
|
StackPtr).addReg(FramePtr);
|
|
} else if (MFI->hasVarSizedObjects()) {
|
|
if (CSSize) {
|
|
unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
|
|
MachineInstr *MI =
|
|
addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
|
|
FramePtr, false, -CSSize);
|
|
MBB.insert(MBBI, MI);
|
|
} else {
|
|
BuildMI(MBB, MBBI, DL,
|
|
TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
|
|
.addReg(FramePtr);
|
|
}
|
|
} else if (NumBytes) {
|
|
// Adjust stack pointer back: ESP += numbytes.
|
|
emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII, *RegInfo);
|
|
}
|
|
|
|
// We're returning from function via eh_return.
|
|
if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
|
|
MBBI = MBB.getLastNonDebugInstr();
|
|
MachineOperand &DestAddr = MBBI->getOperand(0);
|
|
assert(DestAddr.isReg() && "Offset should be in register!");
|
|
BuildMI(MBB, MBBI, DL,
|
|
TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
|
|
StackPtr).addReg(DestAddr.getReg());
|
|
} else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
|
|
RetOpcode == X86::TCRETURNmi ||
|
|
RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
|
|
RetOpcode == X86::TCRETURNmi64) {
|
|
bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
|
|
// Tail call return: adjust the stack pointer and jump to callee.
|
|
MBBI = MBB.getLastNonDebugInstr();
|
|
MachineOperand &JumpTarget = MBBI->getOperand(0);
|
|
MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
|
|
assert(StackAdjust.isImm() && "Expecting immediate value.");
|
|
|
|
// Adjust stack pointer.
|
|
int StackAdj = StackAdjust.getImm();
|
|
int MaxTCDelta = X86FI->getTCReturnAddrDelta();
|
|
int Offset = 0;
|
|
assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
|
|
|
|
// Incoporate the retaddr area.
|
|
Offset = StackAdj-MaxTCDelta;
|
|
assert(Offset >= 0 && "Offset should never be negative");
|
|
|
|
if (Offset) {
|
|
// Check for possible merge with preceding ADD instruction.
|
|
Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
|
|
emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII, *RegInfo);
|
|
}
|
|
|
|
// Jump to label or value in register.
|
|
if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
|
|
MachineInstrBuilder MIB =
|
|
BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
|
|
? X86::TAILJMPd : X86::TAILJMPd64));
|
|
if (JumpTarget.isGlobal())
|
|
MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
|
|
JumpTarget.getTargetFlags());
|
|
else {
|
|
assert(JumpTarget.isSymbol());
|
|
MIB.addExternalSymbol(JumpTarget.getSymbolName(),
|
|
JumpTarget.getTargetFlags());
|
|
}
|
|
} else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
|
|
MachineInstrBuilder MIB =
|
|
BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
|
|
? X86::TAILJMPm : X86::TAILJMPm64));
|
|
for (unsigned i = 0; i != 5; ++i)
|
|
MIB.addOperand(MBBI->getOperand(i));
|
|
} else if (RetOpcode == X86::TCRETURNri64) {
|
|
BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
|
|
addReg(JumpTarget.getReg(), RegState::Kill);
|
|
} else {
|
|
BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
|
|
addReg(JumpTarget.getReg(), RegState::Kill);
|
|
}
|
|
|
|
MachineInstr *NewMI = prior(MBBI);
|
|
for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
|
|
NewMI->addOperand(MBBI->getOperand(i));
|
|
|
|
// Delete the pseudo instruction TCRETURN.
|
|
MBB.erase(MBBI);
|
|
} else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
|
|
(X86FI->getTCReturnAddrDelta() < 0)) {
|
|
// Add the return addr area delta back since we are not tail calling.
|
|
int delta = -1*X86FI->getTCReturnAddrDelta();
|
|
MBBI = MBB.getLastNonDebugInstr();
|
|
|
|
// Check for possible merge with preceding ADD instruction.
|
|
delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
|
|
emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII, *RegInfo);
|
|
}
|
|
}
|
|
|
|
int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
|
|
const X86RegisterInfo *RI =
|
|
static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
|
|
uint64_t StackSize = MFI->getStackSize();
|
|
|
|
if (RI->needsStackRealignment(MF)) {
|
|
if (FI < 0) {
|
|
// Skip the saved EBP.
|
|
Offset += RI->getSlotSize();
|
|
} else {
|
|
unsigned Align = MFI->getObjectAlignment(FI);
|
|
assert((-(Offset + StackSize)) % Align == 0);
|
|
Align = 0;
|
|
return Offset + StackSize;
|
|
}
|
|
// FIXME: Support tail calls
|
|
} else {
|
|
if (!hasFP(MF))
|
|
return Offset + StackSize;
|
|
|
|
// Skip the saved EBP.
|
|
Offset += RI->getSlotSize();
|
|
|
|
// Skip the RETADDR move area
|
|
const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
|
|
int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
|
|
if (TailCallReturnAddrDelta < 0)
|
|
Offset -= TailCallReturnAddrDelta;
|
|
}
|
|
|
|
return Offset;
|
|
}
|
|
|
|
bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI,
|
|
const TargetRegisterInfo *TRI) const {
|
|
if (CSI.empty())
|
|
return false;
|
|
|
|
DebugLoc DL = MBB.findDebugLoc(MI);
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
|
|
unsigned SlotSize = STI.is64Bit() ? 8 : 4;
|
|
unsigned FPReg = TRI->getFrameRegister(MF);
|
|
unsigned CalleeFrameSize = 0;
|
|
|
|
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
|
|
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
|
|
|
|
// Push GPRs. It increases frame size.
|
|
unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
|
|
for (unsigned i = CSI.size(); i != 0; --i) {
|
|
unsigned Reg = CSI[i-1].getReg();
|
|
if (!X86::GR64RegClass.contains(Reg) &&
|
|
!X86::GR32RegClass.contains(Reg))
|
|
continue;
|
|
// Add the callee-saved register as live-in. It's killed at the spill.
|
|
MBB.addLiveIn(Reg);
|
|
if (Reg == FPReg)
|
|
// X86RegisterInfo::emitPrologue will handle spilling of frame register.
|
|
continue;
|
|
CalleeFrameSize += SlotSize;
|
|
BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
}
|
|
|
|
X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
|
|
|
|
// Make XMM regs spilled. X86 does not have ability of push/pop XMM.
|
|
// It can be done by spilling XMMs to stack frame.
|
|
// Note that only Win64 ABI might spill XMMs.
|
|
for (unsigned i = CSI.size(); i != 0; --i) {
|
|
unsigned Reg = CSI[i-1].getReg();
|
|
if (X86::GR64RegClass.contains(Reg) ||
|
|
X86::GR32RegClass.contains(Reg))
|
|
continue;
|
|
// Add the callee-saved register as live-in. It's killed at the spill.
|
|
MBB.addLiveIn(Reg);
|
|
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
|
|
TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
|
|
RC, TRI);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI,
|
|
const TargetRegisterInfo *TRI) const {
|
|
if (CSI.empty())
|
|
return false;
|
|
|
|
DebugLoc DL = MBB.findDebugLoc(MI);
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
|
|
|
|
// Reload XMMs from stack frame.
|
|
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
|
unsigned Reg = CSI[i].getReg();
|
|
if (X86::GR64RegClass.contains(Reg) ||
|
|
X86::GR32RegClass.contains(Reg))
|
|
continue;
|
|
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
|
|
TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
|
|
RC, TRI);
|
|
}
|
|
|
|
// POP GPRs.
|
|
unsigned FPReg = TRI->getFrameRegister(MF);
|
|
unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
|
|
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
|
unsigned Reg = CSI[i].getReg();
|
|
if (!X86::GR64RegClass.contains(Reg) &&
|
|
!X86::GR32RegClass.contains(Reg))
|
|
continue;
|
|
if (Reg == FPReg)
|
|
// X86RegisterInfo::emitEpilogue will handle restoring of frame register.
|
|
continue;
|
|
BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
void
|
|
X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
|
RegScavenger *RS) const {
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
|
|
unsigned SlotSize = RegInfo->getSlotSize();
|
|
|
|
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
|
|
int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
|
|
|
|
if (TailCallReturnAddrDelta < 0) {
|
|
// create RETURNADDR area
|
|
// arg
|
|
// arg
|
|
// RETADDR
|
|
// { ...
|
|
// RETADDR area
|
|
// ...
|
|
// }
|
|
// [EBP]
|
|
MFI->CreateFixedObject(-TailCallReturnAddrDelta,
|
|
(-1U*SlotSize)+TailCallReturnAddrDelta, true);
|
|
}
|
|
|
|
if (hasFP(MF)) {
|
|
assert((TailCallReturnAddrDelta <= 0) &&
|
|
"The Delta should always be zero or negative");
|
|
const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
|
|
|
|
// Create a frame entry for the EBP register that must be saved.
|
|
int FrameIdx = MFI->CreateFixedObject(SlotSize,
|
|
-(int)SlotSize +
|
|
TFI.getOffsetOfLocalArea() +
|
|
TailCallReturnAddrDelta,
|
|
true);
|
|
assert(FrameIdx == MFI->getObjectIndexBegin() &&
|
|
"Slot for EBP register must be last in order to be found!");
|
|
FrameIdx = 0;
|
|
}
|
|
}
|