Cameron McInally 0e6ec124d5 Add an intrinsic for the SSE2 PAUSE instruction. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195697 91177308-0d34-0410-b5e6-96231b3b80d8

2013-11-26 00:20:43 +00:00

..

AArch64

Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 and vector types.

2013-11-22 08:47:22 +00:00

ARM

[ARM] Enable FeatureMP for Cortex-A5 by default.

2013-11-25 13:17:15 +00:00

CPP

[tests] Cleanup initialization of test suffixes.

2013-08-16 00:37:11 +00:00

Generic

Revert r195317 (and r195333), "Teach ISel not to optimize 'optnone' functions."

2013-11-21 10:55:15 +00:00

Hexagon

Debug Info: update testing cases to specify the debug info version number.

2013-11-22 21:49:45 +00:00

Inputs

Debug Info: update testing cases to specify the debug info version number.

2013-11-22 21:49:45 +00:00

Mips

Fixed tryFoldToZero() for vector types that need expansion.

2013-11-25 11:14:43 +00:00

MSP430

Make sure SP is always aligned on a 2 byte boundary

2013-10-24 09:32:31 +00:00

NVPTX

[NVPTX] Fix handling of indirect calls

2013-11-15 12:30:04 +00:00

PowerPC

Debug Info: update testing cases to specify the debug info version number.

2013-11-22 21:49:45 +00:00

R600

R600/SI: Fixing handling of condition codes

2013-11-22 23:07:58 +00:00

SPARC

[Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64.

2013-11-24 20:23:25 +00:00

SystemZ

[SystemZ] Fix TMHH and TMHL usage for z10 with -O0

2013-11-22 17:28:28 +00:00

Thumb

Debug Info: update testing cases to specify the debug info version number.

2013-11-22 21:49:45 +00:00

Thumb2

Enable generating legacy IT block for AArch32

2013-11-13 18:29:49 +00:00

X86

Add an intrinsic for the SSE2 PAUSE instruction.

2013-11-26 00:20:43 +00:00

XCore

Error if we see an alias to a declaration.

2013-11-14 13:58:06 +00:00