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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37741 91177308-0d34-0410-b5e6-96231b3b80d8
623 lines
25 KiB
C++
623 lines
25 KiB
C++
//===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes an abstract interface used to get information about a
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// target machines register file. This information is used for a variety of
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// purposed, especially register allocation.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_MREGISTERINFO_H
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#define LLVM_TARGET_MREGISTERINFO_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include <cassert>
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#include <functional>
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namespace llvm {
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class BitVector;
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class CalleeSavedInfo;
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class MachineFunction;
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class MachineInstr;
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class MachineLocation;
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class MachineMove;
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class RegScavenger;
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class TargetRegisterClass;
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class Type;
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/// TargetRegisterDesc - This record contains all of the information known about
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/// a particular register. The AliasSet field (if not null) contains a pointer
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/// to a Zero terminated array of registers that this register aliases. This is
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/// needed for architectures like X86 which have AL alias AX alias EAX.
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/// Registers that this does not apply to simply should set this to null.
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/// The SubRegs field is a zero terminated array of registers that are
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/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
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/// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate
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/// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH,
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/// AL which are immediate sub-registers of AX. The SuperRegs field is a zero
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/// terminated array of registers that are super-registers of the specific
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/// register, e.g. RAX, EAX, are super-registers of AX.
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///
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struct TargetRegisterDesc {
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const char *Name; // Assembly language name for the register
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const unsigned *AliasSet; // Register Alias Set, described above
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const unsigned *SubRegs; // Sub-register set, described above
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const unsigned *ImmSubRegs; // Immediate sub-register set, described above
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const unsigned *SuperRegs; // Super-register set, described above
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};
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class TargetRegisterClass {
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public:
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typedef const unsigned* iterator;
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typedef const unsigned* const_iterator;
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typedef const MVT::ValueType* vt_iterator;
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typedef const TargetRegisterClass* const * sc_iterator;
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private:
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unsigned ID;
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bool isSubClass;
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const vt_iterator VTs;
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const sc_iterator SubClasses;
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const sc_iterator SuperClasses;
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const sc_iterator SubRegClasses;
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const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
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const iterator RegsBegin, RegsEnd;
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public:
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TargetRegisterClass(unsigned id,
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const MVT::ValueType *vts,
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const TargetRegisterClass * const *subcs,
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const TargetRegisterClass * const *supcs,
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const TargetRegisterClass * const *subregcs,
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unsigned RS, unsigned Al, iterator RB, iterator RE)
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: ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
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SubRegClasses(subregcs),
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RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
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virtual ~TargetRegisterClass() {} // Allow subclasses
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/// getID() - Return the register class ID number.
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///
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unsigned getID() const { return ID; }
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/// begin/end - Return all of the registers in this class.
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///
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iterator begin() const { return RegsBegin; }
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iterator end() const { return RegsEnd; }
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/// getNumRegs - Return the number of registers in this class.
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///
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unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
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/// getRegister - Return the specified register in the class.
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///
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unsigned getRegister(unsigned i) const {
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assert(i < getNumRegs() && "Register number out of range!");
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return RegsBegin[i];
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}
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/// contains - Return true if the specified register is included in this
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/// register class.
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bool contains(unsigned Reg) const {
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for (iterator I = begin(), E = end(); I != E; ++I)
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if (*I == Reg) return true;
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return false;
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}
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/// hasType - return true if this TargetRegisterClass has the ValueType vt.
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///
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bool hasType(MVT::ValueType vt) const {
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for(int i = 0; VTs[i] != MVT::Other; ++i)
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if (VTs[i] == vt)
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return true;
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return false;
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}
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/// vt_begin / vt_end - Loop over all of the value types that can be
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/// represented by values in this register class.
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vt_iterator vt_begin() const {
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return VTs;
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}
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vt_iterator vt_end() const {
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vt_iterator I = VTs;
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while (*I != MVT::Other) ++I;
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return I;
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}
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/// hasSubRegClass - return true if the specified TargetRegisterClass is a
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/// sub-register class of this TargetRegisterClass.
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bool hasSubRegClass(const TargetRegisterClass *cs) const {
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for (int i = 0; SubClasses[i] != NULL; ++i)
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if (SubClasses[i] == cs)
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return true;
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return false;
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}
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/// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
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/// this register class.
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sc_iterator subclasses_begin() const {
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return SubClasses;
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}
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sc_iterator subclasses_end() const {
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sc_iterator I = SubClasses;
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while (*I != NULL) ++I;
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return I;
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}
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/// hasSuperRegClass - return true if the specified TargetRegisterClass is a
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/// super-register class of this TargetRegisterClass.
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bool hasSuperRegClass(const TargetRegisterClass *cs) const {
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for (int i = 0; SuperClasses[i] != NULL; ++i)
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if (SuperClasses[i] == cs)
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return true;
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return false;
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}
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/// superclasses_begin / superclasses_end - Loop over all of the super-classes
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/// of this register class.
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sc_iterator superclasses_begin() const {
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return SuperClasses;
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}
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sc_iterator superclasses_end() const {
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sc_iterator I = SuperClasses;
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while (*I != NULL) ++I;
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return I;
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}
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/// hasSubRegForClass - return true if the specified TargetRegisterClass is a
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/// class of a sub-register class for this TargetRegisterClass.
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bool hasSubRegForClass(const TargetRegisterClass *cs) const {
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for (int i = 0; SubRegClasses[i] != NULL; ++i)
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if (SubRegClasses[i] == cs)
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return true;
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return false;
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}
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/// hasClassForSubReg - return true if the specified TargetRegisterClass is a
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/// class of a sub-register class for this TargetRegisterClass.
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bool hasClassForSubReg(unsigned SubReg) const {
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--SubReg;
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for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
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if (i == SubReg)
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return true;
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return false;
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}
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/// getClassForSubReg - return theTargetRegisterClass for the sub-register
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/// at idx for this TargetRegisterClass.
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sc_iterator getClassForSubReg(unsigned SubReg) const {
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--SubReg;
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for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
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if (i == SubReg)
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return &SubRegClasses[i];
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return NULL;
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}
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/// subregclasses_begin / subregclasses_end - Loop over all of
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/// the subregister classes of this register class.
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sc_iterator subregclasses_begin() const {
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return SubRegClasses;
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}
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sc_iterator subregclasses_end() const {
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sc_iterator I = SubRegClasses;
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while (*I != NULL) ++I;
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return I;
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}
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/// allocation_order_begin/end - These methods define a range of registers
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/// which specify the registers in this class that are valid to register
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/// allocate, and the preferred order to allocate them in. For example,
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/// callee saved registers should be at the end of the list, because it is
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/// cheaper to allocate caller saved registers.
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///
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/// These methods take a MachineFunction argument, which can be used to tune
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/// the allocatable registers based on the characteristics of the function.
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/// One simple example is that the frame pointer register can be used if
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/// frame-pointer-elimination is performed.
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///
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/// By default, these methods return all registers in the class.
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///
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virtual iterator allocation_order_begin(const MachineFunction &MF) const {
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return begin();
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}
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virtual iterator allocation_order_end(const MachineFunction &MF) const {
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return end();
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}
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/// getSize - Return the size of the register in bytes, which is also the size
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/// of a stack slot allocated to hold a spilled copy of this register.
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unsigned getSize() const { return RegSize; }
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/// getAlignment - Return the minimum required alignment for a register of
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/// this class.
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unsigned getAlignment() const { return Alignment; }
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};
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/// MRegisterInfo base class - We assume that the target defines a static array
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/// of TargetRegisterDesc objects that represent all of the machine registers
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/// that the target has. As such, we simply have to track a pointer to this
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/// array so that we can turn register number into a register descriptor.
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///
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class MRegisterInfo {
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public:
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typedef const TargetRegisterClass * const * regclass_iterator;
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private:
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const TargetRegisterDesc *Desc; // Pointer to the descriptor array
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unsigned NumRegs; // Number of entries in the array
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regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
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int CallFrameSetupOpcode, CallFrameDestroyOpcode;
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protected:
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MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
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regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
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int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
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virtual ~MRegisterInfo();
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public:
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enum { // Define some target independent constants
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/// NoRegister - This physical register is not a real target register. It
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/// is useful as a sentinal.
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NoRegister = 0,
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/// FirstVirtualRegister - This is the first register number that is
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/// considered to be a 'virtual' register, which is part of the SSA
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/// namespace. This must be the same for all targets, which means that each
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/// target is limited to 1024 registers.
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FirstVirtualRegister = 1024
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};
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/// isPhysicalRegister - Return true if the specified register number is in
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/// the physical register namespace.
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static bool isPhysicalRegister(unsigned Reg) {
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assert(Reg && "this is not a register!");
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return Reg < FirstVirtualRegister;
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}
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/// isVirtualRegister - Return true if the specified register number is in
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/// the virtual register namespace.
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static bool isVirtualRegister(unsigned Reg) {
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assert(Reg && "this is not a register!");
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return Reg >= FirstVirtualRegister;
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}
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/// getAllocatableSet - Returns a bitset indexed by register number
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/// indicating if a register is allocatable or not. If a register class is
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/// specified, returns the subset for the class.
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BitVector getAllocatableSet(MachineFunction &MF,
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const TargetRegisterClass *RC = NULL) const;
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const TargetRegisterDesc &operator[](unsigned RegNo) const {
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assert(RegNo < NumRegs &&
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"Attempting to access record for invalid register number!");
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return Desc[RegNo];
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}
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/// Provide a get method, equivalent to [], but more useful if we have a
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/// pointer to this object.
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///
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const TargetRegisterDesc &get(unsigned RegNo) const {
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return operator[](RegNo);
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}
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/// getAliasSet - Return the set of registers aliased by the specified
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/// register, or a null list of there are none. The list returned is zero
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/// terminated.
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///
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const unsigned *getAliasSet(unsigned RegNo) const {
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return get(RegNo).AliasSet;
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}
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/// getSubRegisters - Return the set of registers that are sub-registers of
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/// the specified register, or a null list of there are none. The list
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/// returned is zero terminated.
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///
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const unsigned *getSubRegisters(unsigned RegNo) const {
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return get(RegNo).SubRegs;
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}
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/// getImmediateSubRegisters - Return the set of registers that are immediate
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/// sub-registers of the specified register, or a null list of there are none.
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/// The list returned is zero terminated.
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///
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const unsigned *getImmediateSubRegisters(unsigned RegNo) const {
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return get(RegNo).ImmSubRegs;
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}
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/// getSuperRegisters - Return the set of registers that are super-registers
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/// of the specified register, or a null list of there are none. The list
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/// returned is zero terminated.
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///
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const unsigned *getSuperRegisters(unsigned RegNo) const {
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return get(RegNo).SuperRegs;
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}
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/// getName - Return the symbolic target specific name for the specified
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/// physical register.
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const char *getName(unsigned RegNo) const {
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return get(RegNo).Name;
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}
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/// getNumRegs - Return the number of registers this target has
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/// (useful for sizing arrays holding per register information)
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unsigned getNumRegs() const {
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return NumRegs;
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}
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/// areAliases - Returns true if the two registers alias each other,
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/// false otherwise
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bool areAliases(unsigned regA, unsigned regB) const {
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for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
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if (*Alias == regB) return true;
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return false;
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}
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/// regsOverlap - Returns true if the two registers are equal or alias
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/// each other. The registers may be virtual register.
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bool regsOverlap(unsigned regA, unsigned regB) const {
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if (regA == regB)
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return true;
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if (isVirtualRegister(regA) || isVirtualRegister(regB))
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return false;
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return areAliases(regA, regB);
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}
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/// isSubRegister - Returns true if regB is a sub-register of regA.
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///
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bool isSubRegister(unsigned regA, unsigned regB) const {
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for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
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if (*SR == regB) return true;
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return false;
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}
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/// isSuperRegister - Returns true if regB is a super-register of regA.
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///
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bool isSuperRegister(unsigned regA, unsigned regB) const {
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for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
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if (*SR == regB) return true;
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return false;
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}
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/// getCalleeSavedRegs - Return a null-terminated list of all of the
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/// callee saved registers on this target. The register should be in the
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/// order of desired callee-save stack frame offset. The first register is
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/// closed to the incoming stack pointer if stack grows down, and vice versa.
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virtual const unsigned* getCalleeSavedRegs() const = 0;
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/// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
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/// register classes to spill each callee saved register with. The order and
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/// length of this list match the getCalleeSaveRegs() list.
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virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
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/// getReservedRegs - Returns a bitset indexed by physical register number
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/// indicating if a register is a special register that has particular uses and
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/// should be considered unavailable at all times, e.g. SP, RA. This is used by
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/// register scavenger to determine what registers are free.
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virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
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/// getSubReg - Returns the physical register number of sub-register "Index"
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/// for physical register RegNo.
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virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
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//===--------------------------------------------------------------------===//
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// Register Class Information
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//
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/// Register class iterators
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///
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regclass_iterator regclass_begin() const { return RegClassBegin; }
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regclass_iterator regclass_end() const { return RegClassEnd; }
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unsigned getNumRegClasses() const {
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return regclass_end()-regclass_begin();
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}
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/// getRegClass - Returns the register class associated with the enumeration
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/// value. See class TargetOperandInfo.
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const TargetRegisterClass *getRegClass(unsigned i) const {
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assert(i <= getNumRegClasses() && "Register Class ID out of range");
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return i ? RegClassBegin[i - 1] : NULL;
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}
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//===--------------------------------------------------------------------===//
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// Interfaces used by the register allocator and stack frame
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// manipulation passes to move data around between registers,
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// immediates and memory. FIXME: Move these to TargetInstrInfo.h.
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//
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/// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved
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/// registers and returns true if it isn't possible / profitable to do so by
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/// issuing a series of store instructions via storeRegToStackSlot(). Returns
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/// false otherwise.
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virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const {
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return false;
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}
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/// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
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/// saved registers and returns true if it isn't possible / profitable to do
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/// so by issuing a series of load instructions via loadRegToStackSlot().
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/// Returns false otherwise.
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virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const {
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return false;
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}
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIndex,
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const TargetRegisterClass *RC) const = 0;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const = 0;
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virtual void copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const = 0;
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/// reMaterialize - Re-issue the specified 'original' instruction at the
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/// specific location targeting a new destination register.
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virtual void reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg,
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const MachineInstr *Orig) const = 0;
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/// foldMemoryOperand - Attempt to fold a load or store of the
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/// specified stack slot into the specified machine instruction for
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/// the specified operand. If this is possible, a new instruction
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/// is returned with the specified operand folded, otherwise NULL is
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/// returned. The client is responsible for removing the old
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/// instruction and adding the new one in the instruction stream
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virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
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unsigned OpNum,
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int FrameIndex) const {
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return 0;
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}
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/// targetHandlesStackFrameRounding - Returns true if the target is responsible
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/// for rounding up the stack frame (probably at emitPrologue time).
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virtual bool targetHandlesStackFrameRounding() const {
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return false;
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}
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/// requiresRegisterScavenging - returns true if the target requires (and
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/// can make use of) the register scavenger.
|
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virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
|
|
return false;
|
|
}
|
|
|
|
/// hasFP - Return true if the specified function should have a dedicated frame
|
|
/// pointer register. For most targets this is true only if the function has
|
|
/// variable sized allocas or if frame pointer elimination is disabled.
|
|
virtual bool hasFP(const MachineFunction &MF) const = 0;
|
|
|
|
// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
|
|
// not required, we reserve argument space for call sites in the function
|
|
// immediately on entry to the current function. This eliminates the need for
|
|
// add/sub sp brackets around call sites. Returns true if the call frame is
|
|
// included as part of the stack frame.
|
|
virtual bool hasReservedCallFrame(MachineFunction &MF) const {
|
|
return !hasFP(MF);
|
|
}
|
|
|
|
/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
|
|
/// frame setup/destroy instructions if they exist (-1 otherwise). Some
|
|
/// targets use pseudo instructions in order to abstract away the difference
|
|
/// between operating with a frame pointer and operating without, through the
|
|
/// use of these two instructions.
|
|
///
|
|
int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
|
|
int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
|
|
|
|
|
|
/// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
|
|
/// code insertion to eliminate call frame setup and destroy pseudo
|
|
/// instructions (but only if the Target is using them). It is responsible
|
|
/// for eliminating these instructions, replacing them with concrete
|
|
/// instructions. This method need only be implemented if using call frame
|
|
/// setup/destroy pseudo instructions.
|
|
///
|
|
virtual void
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI) const {
|
|
assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
|
|
"eliminateCallFramePseudoInstr must be implemented if using"
|
|
" call frame setup/destroy pseudo instructions!");
|
|
assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
|
|
}
|
|
|
|
/// processFunctionBeforeCalleeSavedScan - This method is called immediately
|
|
/// before PrologEpilogInserter scans the physical registers used to determine
|
|
/// what callee saved registers should be spilled. This method is optional.
|
|
virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
|
RegScavenger *RS = NULL) const {
|
|
|
|
}
|
|
|
|
/// processFunctionBeforeFrameFinalized - This method is called immediately
|
|
/// before the specified functions frame layout (MF.getFrameInfo()) is
|
|
/// finalized. Once the frame is finalized, MO_FrameIndex operands are
|
|
/// replaced with direct constants. This method is optional.
|
|
///
|
|
virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
|
|
}
|
|
|
|
/// eliminateFrameIndex - This method must be overriden to eliminate abstract
|
|
/// frame indices from instructions which may use them. The instruction
|
|
/// referenced by the iterator contains an MO_FrameIndex operand which must be
|
|
/// eliminated by this method. This method may modify or replace the
|
|
/// specified instruction, as long as it keeps the iterator pointing the the
|
|
/// finished product. SPAdj is the SP adjustment due to call frame setup
|
|
/// instruction. The return value is the number of instructions added to
|
|
/// (negative if removed from) the basic block.
|
|
///
|
|
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
|
int SPAdj, RegScavenger *RS=NULL) const = 0;
|
|
|
|
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
|
|
/// the function. The return value is the number of instructions
|
|
/// added to (negative if removed from) the basic block (entry for prologue).
|
|
///
|
|
virtual void emitPrologue(MachineFunction &MF) const = 0;
|
|
virtual void emitEpilogue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const = 0;
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
/// Debug information queries.
|
|
|
|
/// getDwarfRegNum - Map a target register to an equivalent dwarf register
|
|
/// number. Returns -1 if there is no equivalent value.
|
|
virtual int getDwarfRegNum(unsigned RegNum) const = 0;
|
|
|
|
/// getFrameRegister - This method should return the register used as a base
|
|
/// for values allocated in the current stack frame.
|
|
virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
|
|
|
|
/// getRARegister - This method should return the register where the return
|
|
/// address can be found.
|
|
virtual unsigned getRARegister() const = 0;
|
|
|
|
/// getLocation - This method should return the actual location of a frame
|
|
/// variable given the frame index. The location is returned in ML.
|
|
/// Subclasses should override this method for special handling of frame
|
|
/// variables and call MRegisterInfo::getLocation for the default action.
|
|
virtual void getLocation(MachineFunction &MF, unsigned Index,
|
|
MachineLocation &ML) const;
|
|
|
|
/// getInitialFrameState - Returns a list of machine moves that are assumed
|
|
/// on entry to all functions. Note that LabelID is ignored (assumed to be
|
|
/// the beginning of the function.)
|
|
virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
|
|
};
|
|
|
|
// This is useful when building IndexedMaps keyed on virtual registers
|
|
struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
|
|
unsigned operator()(unsigned Reg) const {
|
|
return Reg - MRegisterInfo::FirstVirtualRegister;
|
|
}
|
|
};
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|