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https://github.com/c64scene-ar/llvm-6502.git
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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
90 lines
3.2 KiB
LLVM
90 lines
3.2 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=SI -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s
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declare void @llvm.AMDGPU.barrier.local() noduplicate nounwind
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; SI-LABEL: {{^}}private_access_f64_alloca:
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; SI-ALLOCA: buffer_store_dwordx2
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; SI-ALLOCA: buffer_load_dwordx2
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; SI-PROMOTE: ds_write_b64
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; SI-PROMOTE: ds_read_b64
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define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in, i32 %b) nounwind {
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%val = load double addrspace(1)* %in, align 8
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%array = alloca double, i32 16, align 8
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%ptr = getelementptr double* %array, i32 %b
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store double %val, double* %ptr, align 8
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call void @llvm.AMDGPU.barrier.local() noduplicate nounwind
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%result = load double* %ptr, align 8
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store double %result, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}private_access_v2f64_alloca:
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; SI-ALLOCA: buffer_store_dwordx4
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; SI-ALLOCA: buffer_load_dwordx4
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_read_b32
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define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) nounwind {
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%val = load <2 x double> addrspace(1)* %in, align 16
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%array = alloca <2 x double>, i32 16, align 16
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%ptr = getelementptr <2 x double>* %array, i32 %b
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store <2 x double> %val, <2 x double>* %ptr, align 16
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call void @llvm.AMDGPU.barrier.local() noduplicate nounwind
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%result = load <2 x double>* %ptr, align 16
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store <2 x double> %result, <2 x double> addrspace(1)* %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}private_access_i64_alloca:
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; SI-ALLOCA: buffer_store_dwordx2
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; SI-ALLOCA: buffer_load_dwordx2
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; SI-PROMOTE: ds_write_b64
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; SI-PROMOTE: ds_read_b64
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define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i32 %b) nounwind {
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%val = load i64 addrspace(1)* %in, align 8
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%array = alloca i64, i32 16, align 8
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%ptr = getelementptr i64* %array, i32 %b
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store i64 %val, i64* %ptr, align 8
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call void @llvm.AMDGPU.barrier.local() noduplicate nounwind
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%result = load i64* %ptr, align 8
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store i64 %result, i64 addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}private_access_v2i64_alloca:
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; SI-ALLOCA: buffer_store_dwordx4
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; SI-ALLOCA: buffer_load_dwordx4
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_write_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_read_b32
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; SI-PROMOTE: ds_read_b32
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define void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) nounwind {
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%val = load <2 x i64> addrspace(1)* %in, align 16
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%array = alloca <2 x i64>, i32 16, align 16
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%ptr = getelementptr <2 x i64>* %array, i32 %b
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store <2 x i64> %val, <2 x i64>* %ptr, align 16
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call void @llvm.AMDGPU.barrier.local() noduplicate nounwind
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%result = load <2 x i64>* %ptr, align 16
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out, align 16
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ret void
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}
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