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This way of using getNextOperandForReg() was unlikely to work as intended. We don't give any guarantees about the order of operands in the use-def chains, so looking only at operands following a given operand in the chain doesn't make sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161542 91177308-0d34-0410-b5e6-96231b3b80d8
725 lines
26 KiB
C++
725 lines
26 KiB
C++
//===-- PPCCTRLoops.cpp - Identify and generate CTR loops -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass identifies loops where we can generate the PPC branch instructions
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// that decrement and test the count register (CTR) (bdnz and friends).
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// This pass is based on the HexagonHardwareLoops pass.
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//
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// The pattern that defines the induction variable can changed depending on
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// prior optimizations. For example, the IndVarSimplify phase run by 'opt'
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// normalizes induction variables, and the Loop Strength Reduction pass
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// run by 'llc' may also make changes to the induction variable.
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// The pattern detected by this phase is due to running Strength Reduction.
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//
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// Criteria for CTR loops:
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// - Countable loops (w/ ind. var for a trip count)
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// - Assumes loops are normalized by IndVarSimplify
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// - Try inner-most loops first
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// - No nested CTR loops.
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// - No function calls in loops.
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//
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// Note: As with unconverted loops, PPCBranchSelector must be run after this
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// pass in order to convert long-displacement jumps into jump pairs.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "ctrloops"
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#include "PPC.h"
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#include "PPCTargetMachine.h"
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#include "MCTargetDesc/PPCPredicates.h"
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#include "llvm/Constants.h"
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#include "llvm/PassSupport.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include <algorithm>
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using namespace llvm;
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STATISTIC(NumCTRLoops, "Number of loops converted to CTR loops");
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namespace {
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class CountValue;
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struct PPCCTRLoops : public MachineFunctionPass {
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MachineLoopInfo *MLI;
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MachineRegisterInfo *MRI;
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const TargetInstrInfo *TII;
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public:
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static char ID; // Pass identification, replacement for typeid
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PPCCTRLoops() : MachineFunctionPass(ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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const char *getPassName() const { return "PPC CTR Loops"; }
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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/// getCanonicalInductionVariable - Check to see if the loop has a canonical
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/// induction variable.
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/// Should be defined in MachineLoop. Based upon version in class Loop.
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void getCanonicalInductionVariable(MachineLoop *L,
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SmallVector<MachineInstr *, 4> &IVars,
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SmallVector<MachineInstr *, 4> &IOps) const;
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/// getTripCount - Return a loop-invariant LLVM register indicating the
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/// number of times the loop will be executed. If the trip-count cannot
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/// be determined, this return null.
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CountValue *getTripCount(MachineLoop *L,
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SmallVector<MachineInstr *, 2> &OldInsts) const;
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/// isInductionOperation - Return true if the instruction matches the
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/// pattern for an opertion that defines an induction variable.
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bool isInductionOperation(const MachineInstr *MI, unsigned IVReg) const;
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/// isInvalidOperation - Return true if the instruction is not valid within
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/// a CTR loop.
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bool isInvalidLoopOperation(const MachineInstr *MI) const;
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/// containsInavlidInstruction - Return true if the loop contains an
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/// instruction that inhibits using the CTR loop.
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bool containsInvalidInstruction(MachineLoop *L) const;
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/// converToCTRLoop - Given a loop, check if we can convert it to a
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/// CTR loop. If so, then perform the conversion and return true.
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bool convertToCTRLoop(MachineLoop *L);
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/// isDead - Return true if the instruction is now dead.
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bool isDead(const MachineInstr *MI,
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SmallVector<MachineInstr *, 1> &DeadPhis) const;
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/// removeIfDead - Remove the instruction if it is now dead.
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void removeIfDead(MachineInstr *MI);
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};
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char PPCCTRLoops::ID = 0;
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// CountValue class - Abstraction for a trip count of a loop. A
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// smaller vesrsion of the MachineOperand class without the concerns
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// of changing the operand representation.
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class CountValue {
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public:
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enum CountValueType {
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CV_Register,
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CV_Immediate
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};
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private:
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CountValueType Kind;
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union Values {
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unsigned RegNum;
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int64_t ImmVal;
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Values(unsigned r) : RegNum(r) {}
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Values(int64_t i) : ImmVal(i) {}
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} Contents;
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bool isNegative;
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public:
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CountValue(unsigned r, bool neg) : Kind(CV_Register), Contents(r),
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isNegative(neg) {}
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explicit CountValue(int64_t i) : Kind(CV_Immediate), Contents(i),
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isNegative(i < 0) {}
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CountValueType getType() const { return Kind; }
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bool isReg() const { return Kind == CV_Register; }
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bool isImm() const { return Kind == CV_Immediate; }
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bool isNeg() const { return isNegative; }
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unsigned getReg() const {
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assert(isReg() && "Wrong CountValue accessor");
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return Contents.RegNum;
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}
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void setReg(unsigned Val) {
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Contents.RegNum = Val;
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}
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int64_t getImm() const {
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assert(isImm() && "Wrong CountValue accessor");
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if (isNegative) {
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return -Contents.ImmVal;
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}
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return Contents.ImmVal;
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}
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void setImm(int64_t Val) {
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Contents.ImmVal = Val;
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}
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void print(raw_ostream &OS, const TargetMachine *TM = 0) const {
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if (isReg()) { OS << PrintReg(getReg()); }
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if (isImm()) { OS << getImm(); }
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}
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};
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} // end anonymous namespace
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/// isCompareEquals - Returns true if the instruction is a compare equals
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/// instruction with an immediate operand.
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static bool isCompareEqualsImm(const MachineInstr *MI, bool &SignedCmp) {
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if (MI->getOpcode() == PPC::CMPWI || MI->getOpcode() == PPC::CMPDI) {
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SignedCmp = true;
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return true;
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} else if (MI->getOpcode() == PPC::CMPLWI || MI->getOpcode() == PPC::CMPLDI) {
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SignedCmp = false;
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return true;
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}
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return false;
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}
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/// createPPCCTRLoops - Factory for creating
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/// the CTR loop phase.
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FunctionPass *llvm::createPPCCTRLoops() {
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return new PPCCTRLoops();
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}
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bool PPCCTRLoops::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "********* PPC CTR Loops *********\n");
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bool Changed = false;
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// get the loop information
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MLI = &getAnalysis<MachineLoopInfo>();
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// get the register information
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MRI = &MF.getRegInfo();
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// the target specific instructio info.
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TII = MF.getTarget().getInstrInfo();
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for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end();
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I != E; ++I) {
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MachineLoop *L = *I;
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if (!L->getParentLoop()) {
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Changed |= convertToCTRLoop(L);
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}
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}
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return Changed;
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}
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/// getCanonicalInductionVariable - Check to see if the loop has a canonical
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/// induction variable. We check for a simple recurrence pattern - an
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/// integer recurrence that decrements by one each time through the loop and
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/// ends at zero. If so, return the phi node that corresponds to it.
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///
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/// Based upon the similar code in LoopInfo except this code is specific to
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/// the machine.
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/// This method assumes that the IndVarSimplify pass has been run by 'opt'.
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///
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void
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PPCCTRLoops::getCanonicalInductionVariable(MachineLoop *L,
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SmallVector<MachineInstr *, 4> &IVars,
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SmallVector<MachineInstr *, 4> &IOps) const {
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MachineBasicBlock *TopMBB = L->getTopBlock();
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MachineBasicBlock::pred_iterator PI = TopMBB->pred_begin();
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assert(PI != TopMBB->pred_end() &&
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"Loop must have more than one incoming edge!");
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MachineBasicBlock *Backedge = *PI++;
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if (PI == TopMBB->pred_end()) return; // dead loop
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MachineBasicBlock *Incoming = *PI++;
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if (PI != TopMBB->pred_end()) return; // multiple backedges?
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// make sure there is one incoming and one backedge and determine which
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// is which.
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if (L->contains(Incoming)) {
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if (L->contains(Backedge))
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return;
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std::swap(Incoming, Backedge);
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} else if (!L->contains(Backedge))
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return;
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// Loop over all of the PHI nodes, looking for a canonical induction variable:
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// - The PHI node is "reg1 = PHI reg2, BB1, reg3, BB2".
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// - The recurrence comes from the backedge.
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// - the definition is an induction operatio.n
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for (MachineBasicBlock::iterator I = TopMBB->begin(), E = TopMBB->end();
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I != E && I->isPHI(); ++I) {
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MachineInstr *MPhi = &*I;
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unsigned DefReg = MPhi->getOperand(0).getReg();
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for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
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// Check each operand for the value from the backedge.
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MachineBasicBlock *MBB = MPhi->getOperand(i+1).getMBB();
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if (L->contains(MBB)) { // operands comes from the backedge
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// Check if the definition is an induction operation.
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MachineInstr *DI = MRI->getVRegDef(MPhi->getOperand(i).getReg());
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if (isInductionOperation(DI, DefReg)) {
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IOps.push_back(DI);
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IVars.push_back(MPhi);
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}
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}
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}
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}
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return;
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}
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/// getTripCount - Return a loop-invariant LLVM value indicating the
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/// number of times the loop will be executed. The trip count can
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/// be either a register or a constant value. If the trip-count
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/// cannot be determined, this returns null.
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///
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/// We find the trip count from the phi instruction that defines the
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/// induction variable. We follow the links to the CMP instruction
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/// to get the trip count.
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///
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/// Based upon getTripCount in LoopInfo.
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///
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CountValue *PPCCTRLoops::getTripCount(MachineLoop *L,
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SmallVector<MachineInstr *, 2> &OldInsts) const {
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MachineBasicBlock *LastMBB = L->getExitingBlock();
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// Don't generate a CTR loop if the loop has more than one exit.
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if (LastMBB == 0)
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return 0;
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MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();
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if (LastI->getOpcode() != PPC::BCC)
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return 0;
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// We need to make sure that this compare is defining the condition
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// register actually used by the terminating branch.
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unsigned PredReg = LastI->getOperand(1).getReg();
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DEBUG(dbgs() << "Examining loop with first terminator: " << *LastI);
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unsigned PredCond = LastI->getOperand(0).getImm();
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if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
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return 0;
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// Check that the loop has a induction variable.
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SmallVector<MachineInstr *, 4> IVars, IOps;
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getCanonicalInductionVariable(L, IVars, IOps);
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for (unsigned i = 0; i < IVars.size(); ++i) {
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MachineInstr *IOp = IOps[i];
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MachineInstr *IV_Inst = IVars[i];
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// Canonical loops will end with a 'cmpwi/cmpdi cr, IV, Imm',
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// if Imm is 0, get the count from the PHI opnd
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// if Imm is -M, than M is the count
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// Otherwise, Imm is the count
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MachineOperand *IV_Opnd;
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const MachineOperand *InitialValue;
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if (!L->contains(IV_Inst->getOperand(2).getMBB())) {
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InitialValue = &IV_Inst->getOperand(1);
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IV_Opnd = &IV_Inst->getOperand(3);
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} else {
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InitialValue = &IV_Inst->getOperand(3);
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IV_Opnd = &IV_Inst->getOperand(1);
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}
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DEBUG(dbgs() << "Considering:\n");
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DEBUG(dbgs() << " induction operation: " << *IOp);
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DEBUG(dbgs() << " induction variable: " << *IV_Inst);
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DEBUG(dbgs() << " initial value: " << *InitialValue << "\n");
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// Look for the cmp instruction to determine if we
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// can get a useful trip count. The trip count can
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// be either a register or an immediate. The location
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// of the value depends upon the type (reg or imm).
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for (MachineRegisterInfo::reg_iterator
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RI = MRI->reg_begin(IV_Opnd->getReg()), RE = MRI->reg_end();
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RI != RE; ++RI) {
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IV_Opnd = &RI.getOperand();
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bool SignedCmp;
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MachineInstr *MI = IV_Opnd->getParent();
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if (L->contains(MI) && isCompareEqualsImm(MI, SignedCmp) &&
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MI->getOperand(0).getReg() == PredReg) {
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OldInsts.push_back(MI);
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OldInsts.push_back(IOp);
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DEBUG(dbgs() << " compare: " << *MI);
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const MachineOperand &MO = MI->getOperand(2);
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assert(MO.isImm() && "IV Cmp Operand should be an immediate");
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int64_t ImmVal;
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if (SignedCmp)
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ImmVal = (short) MO.getImm();
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else
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ImmVal = MO.getImm();
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const MachineInstr *IV_DefInstr = MRI->getVRegDef(IV_Opnd->getReg());
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assert(L->contains(IV_DefInstr->getParent()) &&
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"IV definition should occurs in loop");
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int64_t iv_value = (short) IV_DefInstr->getOperand(2).getImm();
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assert(InitialValue->isReg() && "Expecting register for init value");
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unsigned InitialValueReg = InitialValue->getReg();
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const MachineInstr *DefInstr = MRI->getVRegDef(InitialValueReg);
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// Here we need to look for an immediate load (an li or lis/ori pair).
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if (DefInstr && (DefInstr->getOpcode() == PPC::ORI8 ||
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DefInstr->getOpcode() == PPC::ORI)) {
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int64_t start = (short) DefInstr->getOperand(2).getImm();
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const MachineInstr *DefInstr2 =
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MRI->getVRegDef(DefInstr->getOperand(0).getReg());
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if (DefInstr2 && (DefInstr2->getOpcode() == PPC::LIS8 ||
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DefInstr2->getOpcode() == PPC::LIS)) {
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DEBUG(dbgs() << " initial constant: " << *DefInstr);
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DEBUG(dbgs() << " initial constant: " << *DefInstr2);
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start |= int64_t(short(DefInstr2->getOperand(1).getImm())) << 16;
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int64_t count = ImmVal - start;
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if ((count % iv_value) != 0) {
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return 0;
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}
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return new CountValue(count/iv_value);
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}
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} else if (DefInstr && (DefInstr->getOpcode() == PPC::LI8 ||
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DefInstr->getOpcode() == PPC::LI)) {
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DEBUG(dbgs() << " initial constant: " << *DefInstr);
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int64_t count = ImmVal - int64_t(short(DefInstr->getOperand(1).getImm()));
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if ((count % iv_value) != 0) {
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return 0;
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}
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return new CountValue(count/iv_value);
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} else if (iv_value == 1 || iv_value == -1) {
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// We can't determine a constant starting value.
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if (ImmVal == 0) {
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return new CountValue(InitialValueReg, iv_value > 0);
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}
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// FIXME: handle non-zero end value.
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}
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// FIXME: handle non-unit increments (we might not want to introduce division
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// but we can handle some 2^n cases with shifts).
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}
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}
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}
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return 0;
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}
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/// isInductionOperation - return true if the operation is matches the
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/// pattern that defines an induction variable:
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/// addi iv, c
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///
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bool
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PPCCTRLoops::isInductionOperation(const MachineInstr *MI,
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unsigned IVReg) const {
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return ((MI->getOpcode() == PPC::ADDI || MI->getOpcode() == PPC::ADDI8) &&
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MI->getOperand(1).isReg() && // could be a frame index instead
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MI->getOperand(1).getReg() == IVReg);
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}
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/// isInvalidOperation - Return true if the operation is invalid within
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/// CTR loop.
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bool
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PPCCTRLoops::isInvalidLoopOperation(const MachineInstr *MI) const {
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// call is not allowed because the callee may use a CTR loop
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if (MI->getDesc().isCall()) {
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return true;
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}
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// check if the instruction defines a CTR loop register
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// (this will also catch nested CTR loops)
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDef() &&
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(MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8)) {
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return true;
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}
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}
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return false;
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}
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/// containsInvalidInstruction - Return true if the loop contains
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/// an instruction that inhibits the use of the CTR loop function.
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///
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bool PPCCTRLoops::containsInvalidInstruction(MachineLoop *L) const {
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const std::vector<MachineBasicBlock*> Blocks = L->getBlocks();
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for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
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MachineBasicBlock *MBB = Blocks[i];
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for (MachineBasicBlock::iterator
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MII = MBB->begin(), E = MBB->end(); MII != E; ++MII) {
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const MachineInstr *MI = &*MII;
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if (isInvalidLoopOperation(MI)) {
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return true;
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}
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}
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}
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return false;
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}
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/// isDead returns true if the instruction is dead
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/// (this was essentially copied from DeadMachineInstructionElim::isDead, but
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/// with special cases for inline asm, physical registers and instructions with
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/// side effects removed)
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bool PPCCTRLoops::isDead(const MachineInstr *MI,
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SmallVector<MachineInstr *, 1> &DeadPhis) const {
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|
// Examine each operand.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDef()) {
|
|
unsigned Reg = MO.getReg();
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|
if (!MRI->use_nodbg_empty(Reg)) {
|
|
// This instruction has users, but if the only user is the phi node for the
|
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// parent block, and the only use of that phi node is this instruction, then
|
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// this instruction is dead: both it (and the phi node) can be removed.
|
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MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg);
|
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if (llvm::next(I) == MRI->use_end() &&
|
|
I.getOperand().getParent()->isPHI()) {
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|
MachineInstr *OnePhi = I.getOperand().getParent();
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|
|
|
for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) {
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const MachineOperand &OPO = OnePhi->getOperand(j);
|
|
if (OPO.isReg() && OPO.isDef()) {
|
|
unsigned OPReg = OPO.getReg();
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|
|
|
MachineRegisterInfo::use_iterator nextJ;
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for (MachineRegisterInfo::use_iterator J = MRI->use_begin(OPReg),
|
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E = MRI->use_end(); J!=E; J=nextJ) {
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|
nextJ = llvm::next(J);
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|
MachineOperand& Use = J.getOperand();
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|
MachineInstr *UseMI = Use.getParent();
|
|
|
|
if (MI != UseMI) {
|
|
// The phi node has a user that is not MI, bail...
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
DeadPhis.push_back(OnePhi);
|
|
} else {
|
|
// This def has a non-debug use. Don't delete the instruction!
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// If there are no defs with uses, the instruction is dead.
|
|
return true;
|
|
}
|
|
|
|
void PPCCTRLoops::removeIfDead(MachineInstr *MI) {
|
|
// This procedure was essentially copied from DeadMachineInstructionElim
|
|
|
|
SmallVector<MachineInstr *, 1> DeadPhis;
|
|
if (isDead(MI, DeadPhis)) {
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|
DEBUG(dbgs() << "CTR looping will remove: " << *MI);
|
|
|
|
// It is possible that some DBG_VALUE instructions refer to this
|
|
// instruction. Examine each def operand for such references;
|
|
// if found, mark the DBG_VALUE as undef (but don't delete it).
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || !MO.isDef())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
MachineRegisterInfo::use_iterator nextI;
|
|
for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
|
|
E = MRI->use_end(); I!=E; I=nextI) {
|
|
nextI = llvm::next(I); // I is invalidated by the setReg
|
|
MachineOperand& Use = I.getOperand();
|
|
MachineInstr *UseMI = Use.getParent();
|
|
if (UseMI==MI)
|
|
continue;
|
|
if (Use.isDebug()) // this might also be a instr -> phi -> instr case
|
|
// which can also be removed.
|
|
UseMI->getOperand(0).setReg(0U);
|
|
}
|
|
}
|
|
|
|
MI->eraseFromParent();
|
|
for (unsigned i = 0; i < DeadPhis.size(); ++i) {
|
|
DeadPhis[i]->eraseFromParent();
|
|
}
|
|
}
|
|
}
|
|
|
|
/// converToCTRLoop - check if the loop is a candidate for
|
|
/// converting to a CTR loop. If so, then perform the
|
|
/// transformation.
|
|
///
|
|
/// This function works on innermost loops first. A loop can
|
|
/// be converted if it is a counting loop; either a register
|
|
/// value or an immediate.
|
|
///
|
|
/// The code makes several assumptions about the representation
|
|
/// of the loop in llvm.
|
|
bool PPCCTRLoops::convertToCTRLoop(MachineLoop *L) {
|
|
bool Changed = false;
|
|
// Process nested loops first.
|
|
for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) {
|
|
Changed |= convertToCTRLoop(*I);
|
|
}
|
|
// If a nested loop has been converted, then we can't convert this loop.
|
|
if (Changed) {
|
|
return Changed;
|
|
}
|
|
|
|
SmallVector<MachineInstr *, 2> OldInsts;
|
|
// Are we able to determine the trip count for the loop?
|
|
CountValue *TripCount = getTripCount(L, OldInsts);
|
|
if (TripCount == 0) {
|
|
DEBUG(dbgs() << "failed to get trip count!\n");
|
|
return false;
|
|
}
|
|
// Does the loop contain any invalid instructions?
|
|
if (containsInvalidInstruction(L)) {
|
|
return false;
|
|
}
|
|
MachineBasicBlock *Preheader = L->getLoopPreheader();
|
|
// No preheader means there's not place for the loop instr.
|
|
if (Preheader == 0) {
|
|
return false;
|
|
}
|
|
MachineBasicBlock::iterator InsertPos = Preheader->getFirstTerminator();
|
|
|
|
DebugLoc dl;
|
|
if (InsertPos != Preheader->end())
|
|
dl = InsertPos->getDebugLoc();
|
|
|
|
MachineBasicBlock *LastMBB = L->getExitingBlock();
|
|
// Don't generate CTR loop if the loop has more than one exit.
|
|
if (LastMBB == 0) {
|
|
return false;
|
|
}
|
|
MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();
|
|
|
|
// Determine the loop start.
|
|
MachineBasicBlock *LoopStart = L->getTopBlock();
|
|
if (L->getLoopLatch() != LastMBB) {
|
|
// When the exit and latch are not the same, use the latch block as the
|
|
// start.
|
|
// The loop start address is used only after the 1st iteration, and the loop
|
|
// latch may contains instrs. that need to be executed after the 1st iter.
|
|
LoopStart = L->getLoopLatch();
|
|
// Make sure the latch is a successor of the exit, otherwise it won't work.
|
|
if (!LastMBB->isSuccessor(LoopStart)) {
|
|
return false;
|
|
}
|
|
}
|
|
|
|
// Convert the loop to a CTR loop
|
|
DEBUG(dbgs() << "Change to CTR loop at "; L->dump());
|
|
|
|
MachineFunction *MF = LastMBB->getParent();
|
|
const PPCSubtarget &Subtarget = MF->getTarget().getSubtarget<PPCSubtarget>();
|
|
bool isPPC64 = Subtarget.isPPC64();
|
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC;
|
|
|
|
unsigned CountReg;
|
|
if (TripCount->isReg()) {
|
|
// Create a copy of the loop count register.
|
|
const TargetRegisterClass *SrcRC =
|
|
MF->getRegInfo().getRegClass(TripCount->getReg());
|
|
CountReg = MF->getRegInfo().createVirtualRegister(RC);
|
|
unsigned CopyOp = (isPPC64 && SrcRC == GPRC) ?
|
|
(unsigned) PPC::EXTSW_32_64 :
|
|
(unsigned) TargetOpcode::COPY;
|
|
BuildMI(*Preheader, InsertPos, dl,
|
|
TII->get(CopyOp), CountReg).addReg(TripCount->getReg());
|
|
if (TripCount->isNeg()) {
|
|
unsigned CountReg1 = CountReg;
|
|
CountReg = MF->getRegInfo().createVirtualRegister(RC);
|
|
BuildMI(*Preheader, InsertPos, dl,
|
|
TII->get(isPPC64 ? PPC::NEG8 : PPC::NEG),
|
|
CountReg).addReg(CountReg1);
|
|
}
|
|
} else {
|
|
assert(TripCount->isImm() && "Expecting immedate vaule for trip count");
|
|
// Put the trip count in a register for transfer into the count register.
|
|
|
|
int64_t CountImm = TripCount->getImm();
|
|
assert(!TripCount->isNeg() && "Constant trip count must be positive");
|
|
|
|
CountReg = MF->getRegInfo().createVirtualRegister(RC);
|
|
if (CountImm > 0xFFFF) {
|
|
BuildMI(*Preheader, InsertPos, dl,
|
|
TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS),
|
|
CountReg).addImm(CountImm >> 16);
|
|
unsigned CountReg1 = CountReg;
|
|
CountReg = MF->getRegInfo().createVirtualRegister(RC);
|
|
BuildMI(*Preheader, InsertPos, dl,
|
|
TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI),
|
|
CountReg).addReg(CountReg1).addImm(CountImm & 0xFFFF);
|
|
} else {
|
|
BuildMI(*Preheader, InsertPos, dl,
|
|
TII->get(isPPC64 ? PPC::LI8 : PPC::LI),
|
|
CountReg).addImm(CountImm);
|
|
}
|
|
}
|
|
|
|
// Add the mtctr instruction to the beginning of the loop.
|
|
BuildMI(*Preheader, InsertPos, dl,
|
|
TII->get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(CountReg,
|
|
TripCount->isImm() ? RegState::Kill : 0);
|
|
|
|
// Make sure the loop start always has a reference in the CFG. We need to
|
|
// create a BlockAddress operand to get this mechanism to work both the
|
|
// MachineBasicBlock and BasicBlock objects need the flag set.
|
|
LoopStart->setHasAddressTaken();
|
|
// This line is needed to set the hasAddressTaken flag on the BasicBlock
|
|
// object
|
|
BlockAddress::get(const_cast<BasicBlock *>(LoopStart->getBasicBlock()));
|
|
|
|
// Replace the loop branch with a bdnz instruction.
|
|
dl = LastI->getDebugLoc();
|
|
const std::vector<MachineBasicBlock*> Blocks = L->getBlocks();
|
|
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
|
|
MachineBasicBlock *MBB = Blocks[i];
|
|
if (MBB != Preheader)
|
|
MBB->addLiveIn(isPPC64 ? PPC::CTR8 : PPC::CTR);
|
|
}
|
|
|
|
// The loop ends with either:
|
|
// - a conditional branch followed by an unconditional branch, or
|
|
// - a conditional branch to the loop start.
|
|
assert(LastI->getOpcode() == PPC::BCC &&
|
|
"loop end must start with a BCC instruction");
|
|
// Either the BCC branches to the beginning of the loop, or it
|
|
// branches out of the loop and there is an unconditional branch
|
|
// to the start of the loop.
|
|
MachineBasicBlock *BranchTarget = LastI->getOperand(2).getMBB();
|
|
BuildMI(*LastMBB, LastI, dl,
|
|
TII->get((BranchTarget == LoopStart) ?
|
|
(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
|
|
(isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(BranchTarget);
|
|
|
|
// Conditional branch; just delete it.
|
|
DEBUG(dbgs() << "Removing old branch: " << *LastI);
|
|
LastMBB->erase(LastI);
|
|
|
|
delete TripCount;
|
|
|
|
// The induction operation (add) and the comparison (cmpwi) may now be
|
|
// unneeded. If these are unneeded, then remove them.
|
|
for (unsigned i = 0; i < OldInsts.size(); ++i)
|
|
removeIfDead(OldInsts[i]);
|
|
|
|
++NumCTRLoops;
|
|
return true;
|
|
}
|
|
|