mirror of
https://github.com/c64scene-ar/llvm-6502.git
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the compiler makes use of GPR0. However, there are two flavors of GPR0 defined by the target: the 32-bit GPR0 (R0) and the 64-bit GPR0 (X0). The spill/reload code makes use of R0 regardless of whether we are generating 32- or 64-bit code. This patch corrects the problem in the obvious manner, using X0 and ADDI8 for 64-bit and R0 and ADDI for 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165658 91177308-0d34-0410-b5e6-96231b3b80d8
796 lines
31 KiB
C++
796 lines
31 KiB
C++
//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCInstrInfo.h"
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#include "PPC.h"
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#include "PPCInstrBuilder.h"
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#include "PPCMachineFunctionInfo.h"
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#include "PPCTargetMachine.h"
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#include "PPCHazardRecognizers.h"
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#include "MCTargetDesc/PPCPredicates.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/STLExtras.h"
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#define GET_INSTRINFO_CTOR
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#include "PPCGenInstrInfo.inc"
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namespace llvm {
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extern cl::opt<bool> DisablePPC32RS;
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extern cl::opt<bool> DisablePPC64RS;
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}
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using namespace llvm;
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static cl::
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opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
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cl::desc("Disable analysis for CTR loops"));
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PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
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: PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
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TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
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/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
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/// this target when scheduling the DAG.
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ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
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const TargetMachine *TM,
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const ScheduleDAG *DAG) const {
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unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
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if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
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Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
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const InstrItineraryData *II = TM->getInstrItineraryData();
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return new PPCScoreboardHazardRecognizer(II, DAG);
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}
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return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
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}
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/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
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/// to use for this target when scheduling the DAG.
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ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
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const InstrItineraryData *II,
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const ScheduleDAG *DAG) const {
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unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
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// Most subtargets use a PPC970 recognizer.
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if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
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Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
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const TargetInstrInfo *TII = TM.getInstrInfo();
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assert(TII && "No InstrInfo?");
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return new PPCHazardRecognizer970(*TII);
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}
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return new PPCScoreboardHazardRecognizer(II, DAG);
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}
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// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
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bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const {
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switch (MI.getOpcode()) {
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default: return false;
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case PPC::EXTSW:
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case PPC::EXTSW_32_64:
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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SubIdx = PPC::sub_32;
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return true;
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}
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}
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unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case PPC::LD:
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case PPC::LWZ:
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case PPC::LFS:
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case PPC::LFD:
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if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
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MI->getOperand(2).isFI()) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case PPC::STD:
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case PPC::STW:
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case PPC::STFS:
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case PPC::STFD:
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if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
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MI->getOperand(2).isFI()) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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// commuteInstruction - We can commute rlwimi instructions, but only if the
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// rotate amt is zero. We also have to munge the immediates a bit.
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MachineInstr *
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PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
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MachineFunction &MF = *MI->getParent()->getParent();
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// Normal instructions can be commuted the obvious way.
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if (MI->getOpcode() != PPC::RLWIMI)
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return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
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// Cannot commute if it has a non-zero rotate count.
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if (MI->getOperand(3).getImm() != 0)
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return 0;
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// If we have a zero rotate count, we have:
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// M = mask(MB,ME)
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// Op0 = (Op1 & ~M) | (Op2 & M)
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// Change this to:
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// M = mask((ME+1)&31, (MB-1)&31)
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// Op0 = (Op2 & ~M) | (Op1 & M)
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// Swap op1/op2
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unsigned Reg0 = MI->getOperand(0).getReg();
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unsigned Reg1 = MI->getOperand(1).getReg();
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unsigned Reg2 = MI->getOperand(2).getReg();
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bool Reg1IsKill = MI->getOperand(1).isKill();
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bool Reg2IsKill = MI->getOperand(2).isKill();
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bool ChangeReg0 = false;
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// If machine instrs are no longer in two-address forms, update
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// destination register as well.
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if (Reg0 == Reg1) {
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// Must be two address instruction!
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assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
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"Expecting a two-address instruction!");
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Reg2IsKill = false;
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ChangeReg0 = true;
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}
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// Masks.
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unsigned MB = MI->getOperand(4).getImm();
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unsigned ME = MI->getOperand(5).getImm();
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if (NewMI) {
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// Create a new instruction.
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unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
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bool Reg0IsDead = MI->getOperand(0).isDead();
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return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
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.addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
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.addReg(Reg2, getKillRegState(Reg2IsKill))
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.addReg(Reg1, getKillRegState(Reg1IsKill))
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.addImm((ME+1) & 31)
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.addImm((MB-1) & 31);
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}
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if (ChangeReg0)
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MI->getOperand(0).setReg(Reg2);
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(1).setReg(Reg2);
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MI->getOperand(2).setIsKill(Reg1IsKill);
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MI->getOperand(1).setIsKill(Reg2IsKill);
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// Swap the mask around.
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MI->getOperand(4).setImm((ME+1) & 31);
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MI->getOperand(5).setImm((MB-1) & 31);
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return MI;
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}
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void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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DebugLoc DL;
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BuildMI(MBB, MI, DL, get(PPC::NOP));
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}
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// Branch analysis.
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// Note: If the condition register is set to CTR or CTR8 then this is a
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// BDNZ (imm == 1) or BDZ (imm == 0) branch.
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bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin())
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return false;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return false;
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--I;
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}
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if (!isUnpredicatedTerminator(I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (LastInst->getOpcode() == PPC::B) {
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if (!LastInst->getOperand(0).isMBB())
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return true;
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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} else if (LastInst->getOpcode() == PPC::BCC) {
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if (!LastInst->getOperand(2).isMBB())
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return true;
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(2).getMBB();
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Cond.push_back(LastInst->getOperand(0));
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Cond.push_back(LastInst->getOperand(1));
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return false;
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} else if (LastInst->getOpcode() == PPC::BDNZ8 ||
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LastInst->getOpcode() == PPC::BDNZ) {
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if (!LastInst->getOperand(0).isMBB())
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return true;
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if (DisableCTRLoopAnal)
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return true;
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TBB = LastInst->getOperand(0).getMBB();
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Cond.push_back(MachineOperand::CreateImm(1));
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Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
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true));
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return false;
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} else if (LastInst->getOpcode() == PPC::BDZ8 ||
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LastInst->getOpcode() == PPC::BDZ) {
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if (!LastInst->getOperand(0).isMBB())
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return true;
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if (DisableCTRLoopAnal)
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return true;
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TBB = LastInst->getOperand(0).getMBB();
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Cond.push_back(MachineOperand::CreateImm(0));
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Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
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true));
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return false;
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}
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// Otherwise, don't know what this is.
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return true;
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}
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// Get the instruction before it if it's a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() &&
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isUnpredicatedTerminator(--I))
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return true;
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// If the block ends with PPC::B and PPC:BCC, handle it.
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if (SecondLastInst->getOpcode() == PPC::BCC &&
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LastInst->getOpcode() == PPC::B) {
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if (!SecondLastInst->getOperand(2).isMBB() ||
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!LastInst->getOperand(0).isMBB())
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return true;
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TBB = SecondLastInst->getOperand(2).getMBB();
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Cond.push_back(SecondLastInst->getOperand(0));
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Cond.push_back(SecondLastInst->getOperand(1));
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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} else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
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SecondLastInst->getOpcode() == PPC::BDNZ) &&
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LastInst->getOpcode() == PPC::B) {
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if (!SecondLastInst->getOperand(0).isMBB() ||
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!LastInst->getOperand(0).isMBB())
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return true;
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if (DisableCTRLoopAnal)
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return true;
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TBB = SecondLastInst->getOperand(0).getMBB();
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Cond.push_back(MachineOperand::CreateImm(1));
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Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
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true));
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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} else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
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SecondLastInst->getOpcode() == PPC::BDZ) &&
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LastInst->getOpcode() == PPC::B) {
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if (!SecondLastInst->getOperand(0).isMBB() ||
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!LastInst->getOperand(0).isMBB())
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return true;
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if (DisableCTRLoopAnal)
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return true;
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TBB = SecondLastInst->getOperand(0).getMBB();
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Cond.push_back(MachineOperand::CreateImm(0));
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Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
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true));
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two PPC:Bs, handle it. The second one is not
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// executed, so remove it.
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if (SecondLastInst->getOpcode() == PPC::B &&
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LastInst->getOpcode() == PPC::B) {
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if (!SecondLastInst->getOperand(0).isMBB())
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return true;
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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if (AllowModify)
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I->eraseFromParent();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return 0;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return 0;
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--I;
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}
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if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
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I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
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I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin()) return 1;
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--I;
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if (I->getOpcode() != PPC::BCC &&
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I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
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I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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}
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unsigned
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PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"PPC branch conditions have two components!");
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bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
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// One-way branch.
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if (FBB == 0) {
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if (Cond.empty()) // Unconditional branch
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BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
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else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
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BuildMI(&MBB, DL, get(Cond[0].getImm() ?
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(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
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(isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
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else // Conditional branch
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BuildMI(&MBB, DL, get(PPC::BCC))
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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return 1;
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}
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// Two-way Conditional Branch.
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if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
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BuildMI(&MBB, DL, get(Cond[0].getImm() ?
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(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
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(isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
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else
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BuildMI(&MBB, DL, get(PPC::BCC))
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
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return 2;
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}
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void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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unsigned Opc;
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if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
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Opc = PPC::OR;
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else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
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Opc = PPC::OR8;
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else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
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Opc = PPC::FMR;
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else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
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Opc = PPC::MCRF;
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else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
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Opc = PPC::VOR;
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else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
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Opc = PPC::CROR;
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else
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llvm_unreachable("Impossible reg-to-reg copy");
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const MCInstrDesc &MCID = get(Opc);
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if (MCID.getNumOperands() == 3)
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BuildMI(MBB, I, DL, MCID, DestReg)
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.addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
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else
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BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
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}
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// This function returns true if a CR spill is necessary and false otherwise.
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|
bool
|
|
PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
|
|
unsigned SrcReg, bool isKill,
|
|
int FrameIdx,
|
|
const TargetRegisterClass *RC,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const{
|
|
DebugLoc DL;
|
|
if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
|
|
if (SrcReg != PPC::LR) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
|
|
.addReg(SrcReg,
|
|
getKillRegState(isKill)),
|
|
FrameIdx));
|
|
} else {
|
|
// FIXME: this spills LR immediately to memory in one step. To do this,
|
|
// we use R11, which we know cannot be used in the prolog/epilog. This is
|
|
// a hack.
|
|
NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
|
|
.addReg(PPC::R11,
|
|
getKillRegState(isKill)),
|
|
FrameIdx));
|
|
}
|
|
} else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
|
|
if (SrcReg != PPC::LR8) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
|
|
.addReg(SrcReg,
|
|
getKillRegState(isKill)),
|
|
FrameIdx));
|
|
} else {
|
|
// FIXME: this spills LR immediately to memory in one step. To do this,
|
|
// we use X11, which we know cannot be used in the prolog/epilog. This is
|
|
// a hack.
|
|
NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
|
|
.addReg(PPC::X11,
|
|
getKillRegState(isKill)),
|
|
FrameIdx));
|
|
}
|
|
} else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
|
|
.addReg(SrcReg,
|
|
getKillRegState(isKill)),
|
|
FrameIdx));
|
|
} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
|
|
.addReg(SrcReg,
|
|
getKillRegState(isKill)),
|
|
FrameIdx));
|
|
} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
|
|
if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
|
|
(!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
|
|
.addReg(SrcReg,
|
|
getKillRegState(isKill)),
|
|
FrameIdx));
|
|
return true;
|
|
} else {
|
|
// FIXME: We need a scatch reg here. The trouble with using R0 is that
|
|
// it's possible for the stack frame to be so big the save location is
|
|
// out of range of immediate offsets, necessitating another register.
|
|
// We hack this on Darwin by reserving R2. It's probably broken on Linux
|
|
// at the moment.
|
|
|
|
bool is64Bit = TM.getSubtargetImpl()->isPPC64();
|
|
// We need to store the CR in the low 4-bits of the saved value. First,
|
|
// issue a MFCR to save all of the CRBits.
|
|
unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
|
|
(is64Bit ? PPC::X2 : PPC::R2) :
|
|
(is64Bit ? PPC::X0 : PPC::R0);
|
|
NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::MFCR8pseud :
|
|
PPC::MFCRpseud), ScratchReg)
|
|
.addReg(SrcReg, getKillRegState(isKill)));
|
|
|
|
// If the saved register wasn't CR0, shift the bits left so that they are
|
|
// in CR0's slot.
|
|
if (SrcReg != PPC::CR0) {
|
|
unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4;
|
|
// rlwinm scratch, scratch, ShiftBits, 0, 31.
|
|
NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::RLWINM8 :
|
|
PPC::RLWINM), ScratchReg)
|
|
.addReg(ScratchReg).addImm(ShiftBits)
|
|
.addImm(0).addImm(31));
|
|
}
|
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(is64Bit ?
|
|
PPC::STW8 : PPC::STW))
|
|
.addReg(ScratchReg,
|
|
getKillRegState(isKill)),
|
|
FrameIdx));
|
|
}
|
|
} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
|
|
// FIXME: We use CRi here because there is no mtcrf on a bit. Since the
|
|
// backend currently only uses CR1EQ as an individual bit, this should
|
|
// not cause any bug. If we need other uses of CR bits, the following
|
|
// code may be invalid.
|
|
unsigned Reg = 0;
|
|
if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
|
|
SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
|
|
Reg = PPC::CR0;
|
|
else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
|
|
SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
|
|
Reg = PPC::CR1;
|
|
else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
|
|
SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
|
|
Reg = PPC::CR2;
|
|
else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
|
|
SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
|
|
Reg = PPC::CR3;
|
|
else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
|
|
SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
|
|
Reg = PPC::CR4;
|
|
else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
|
|
SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
|
|
Reg = PPC::CR5;
|
|
else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
|
|
SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
|
|
Reg = PPC::CR6;
|
|
else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
|
|
SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
|
|
Reg = PPC::CR7;
|
|
|
|
return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
|
|
&PPC::CRRCRegClass, NewMIs);
|
|
|
|
} else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
|
|
// We don't have indexed addressing for vector loads. Emit:
|
|
// R0 = ADDI FI#
|
|
// STVX VAL, 0, R0
|
|
//
|
|
// FIXME: We use R0 here, because it isn't available for RA.
|
|
bool Is64Bit = TM.getSubtargetImpl()->isPPC64();
|
|
unsigned Instr = Is64Bit ? PPC::ADDI8 : PPC::ADDI;
|
|
unsigned GPR0 = Is64Bit ? PPC::X0 : PPC::R0;
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Instr), GPR0),
|
|
FrameIdx, 0, 0));
|
|
NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
|
|
.addReg(SrcReg, getKillRegState(isKill))
|
|
.addReg(GPR0)
|
|
.addReg(GPR0));
|
|
} else {
|
|
llvm_unreachable("Unknown regclass!");
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
void
|
|
PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned SrcReg, bool isKill, int FrameIdx,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const {
|
|
MachineFunction &MF = *MBB.getParent();
|
|
SmallVector<MachineInstr*, 4> NewMIs;
|
|
|
|
if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
|
|
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
|
|
FuncInfo->setSpillsCR();
|
|
}
|
|
|
|
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
|
|
MBB.insert(MI, NewMIs[i]);
|
|
|
|
const MachineFrameInfo &MFI = *MF.getFrameInfo();
|
|
MachineMemOperand *MMO =
|
|
MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
|
|
MachineMemOperand::MOStore,
|
|
MFI.getObjectSize(FrameIdx),
|
|
MFI.getObjectAlignment(FrameIdx));
|
|
NewMIs.back()->addMemOperand(MF, MMO);
|
|
}
|
|
|
|
bool
|
|
PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
|
|
unsigned DestReg, int FrameIdx,
|
|
const TargetRegisterClass *RC,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs)const{
|
|
if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
|
|
if (DestReg != PPC::LR) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
|
|
DestReg), FrameIdx));
|
|
} else {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
|
|
PPC::R11), FrameIdx));
|
|
NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
|
|
}
|
|
} else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
|
|
if (DestReg != PPC::LR8) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
|
|
FrameIdx));
|
|
} else {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
|
|
PPC::X11), FrameIdx));
|
|
NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11));
|
|
}
|
|
} else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
|
|
FrameIdx));
|
|
} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
|
|
FrameIdx));
|
|
} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
|
|
if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
|
|
(!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
|
|
get(PPC::RESTORE_CR), DestReg)
|
|
, FrameIdx));
|
|
return true;
|
|
} else {
|
|
// FIXME: We need a scatch reg here. The trouble with using R0 is that
|
|
// it's possible for the stack frame to be so big the save location is
|
|
// out of range of immediate offsets, necessitating another register.
|
|
// We hack this on Darwin by reserving R2. It's probably broken on Linux
|
|
// at the moment.
|
|
unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
|
|
PPC::R2 : PPC::R0;
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
|
|
ScratchReg), FrameIdx));
|
|
|
|
// If the reloaded register isn't CR0, shift the bits right so that they are
|
|
// in the right CR's slot.
|
|
if (DestReg != PPC::CR0) {
|
|
unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
|
|
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
|
|
NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
|
|
.addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
|
|
.addImm(31));
|
|
}
|
|
|
|
NewMIs.push_back(BuildMI(MF, DL, get(TM.getSubtargetImpl()->isPPC64() ?
|
|
PPC::MTCRF8 : PPC::MTCRF), DestReg)
|
|
.addReg(ScratchReg));
|
|
}
|
|
} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
|
|
|
|
unsigned Reg = 0;
|
|
if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
|
|
DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
|
|
Reg = PPC::CR0;
|
|
else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
|
|
DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
|
|
Reg = PPC::CR1;
|
|
else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
|
|
DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
|
|
Reg = PPC::CR2;
|
|
else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
|
|
DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
|
|
Reg = PPC::CR3;
|
|
else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
|
|
DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
|
|
Reg = PPC::CR4;
|
|
else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
|
|
DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
|
|
Reg = PPC::CR5;
|
|
else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
|
|
DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
|
|
Reg = PPC::CR6;
|
|
else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
|
|
DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
|
|
Reg = PPC::CR7;
|
|
|
|
return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
|
|
&PPC::CRRCRegClass, NewMIs);
|
|
|
|
} else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
|
|
// We don't have indexed addressing for vector loads. Emit:
|
|
// R0 = ADDI FI#
|
|
// Dest = LVX 0, R0
|
|
//
|
|
// FIXME: We use R0 here, because it isn't available for RA.
|
|
bool Is64Bit = TM.getSubtargetImpl()->isPPC64();
|
|
unsigned Instr = Is64Bit ? PPC::ADDI8 : PPC::ADDI;
|
|
unsigned GPR0 = Is64Bit ? PPC::X0 : PPC::R0;
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Instr), GPR0),
|
|
FrameIdx, 0, 0));
|
|
NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(GPR0)
|
|
.addReg(GPR0));
|
|
} else {
|
|
llvm_unreachable("Unknown regclass!");
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
void
|
|
PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned DestReg, int FrameIdx,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const {
|
|
MachineFunction &MF = *MBB.getParent();
|
|
SmallVector<MachineInstr*, 4> NewMIs;
|
|
DebugLoc DL;
|
|
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
|
if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs)) {
|
|
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
|
|
FuncInfo->setSpillsCR();
|
|
}
|
|
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
|
|
MBB.insert(MI, NewMIs[i]);
|
|
|
|
const MachineFrameInfo &MFI = *MF.getFrameInfo();
|
|
MachineMemOperand *MMO =
|
|
MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
|
|
MachineMemOperand::MOLoad,
|
|
MFI.getObjectSize(FrameIdx),
|
|
MFI.getObjectAlignment(FrameIdx));
|
|
NewMIs.back()->addMemOperand(MF, MMO);
|
|
}
|
|
|
|
MachineInstr*
|
|
PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
|
|
int FrameIx, uint64_t Offset,
|
|
const MDNode *MDPtr,
|
|
DebugLoc DL) const {
|
|
MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
|
|
addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
|
|
return &*MIB;
|
|
}
|
|
|
|
bool PPCInstrInfo::
|
|
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
|
|
assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
|
|
if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
|
|
Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
|
|
else
|
|
// Leave the CR# the same, but invert the condition.
|
|
Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
|
|
return false;
|
|
}
|
|
|
|
/// GetInstSize - Return the number of bytes of code the specified
|
|
/// instruction may be. This returns the maximum number of bytes.
|
|
///
|
|
unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
|
|
switch (MI->getOpcode()) {
|
|
case PPC::INLINEASM: { // Inline Asm: Variable size.
|
|
const MachineFunction *MF = MI->getParent()->getParent();
|
|
const char *AsmStr = MI->getOperand(0).getSymbolName();
|
|
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
|
|
}
|
|
case PPC::PROLOG_LABEL:
|
|
case PPC::EH_LABEL:
|
|
case PPC::GC_LABEL:
|
|
case PPC::DBG_VALUE:
|
|
return 0;
|
|
case PPC::BL8_NOP_ELF:
|
|
case PPC::BLA8_NOP_ELF:
|
|
return 8;
|
|
default:
|
|
return 4; // PowerPC instructions are all 4 bytes
|
|
}
|
|
}
|