Jim Grosbach 0d34b1ed26 AArch64: More correctly constrain target vector extend lowering. ... The AArch64 target lowering for [zs]ext of vectors is set up to handle input simple types and expects the generic SDag path to do something reasonable with anything that's not a simple type. The code, however, was only checking that the result type was a simple type and assuming that implied that the source type would also be a simple type. That's not a valid assumption, as operations like "zext <1 x i1> %0 to <1 x i32>" demonstrate. The fix is to simply explicitly validate the source type as well as the result type. PR20791 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216689 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-28 22:08:28 +00:00
..
Analysis
AsmParser
Bitcode
CodeGen	Move FNEG next to FABS and make them more similar, so it's easier that they can be refactored. NFC.	2014-08-28 21:51:37 +00:00
DebugInfo
ExecutionEngine	[MCJIT] Fix format specifiers for debug output in RuntimeDyld.	2014-08-28 04:25:17 +00:00
IR
IRReader
LineEditor
Linker
LTO
MC	Silence a -Wsign-compare warning. NFC.	2014-08-28 13:23:26 +00:00
Object
Option
ProfileData
Support
TableGen
Target	AArch64: More correctly constrain target vector extend lowering.	2014-08-28 22:08:28 +00:00
Transforms	InstCombine: Remove redundant combines	2014-08-28 10:08:37 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile