mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0d51d7bf86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214273 91177308-0d34-0410-b5e6-96231b3b80d8
66 lines
2.0 KiB
LLVM
66 lines
2.0 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s
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;CHECK-LABEL: _inreg16xi32:
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;CHECK: vpbroadcastd {{.*}}, %zmm
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;CHECK: ret
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define <16 x i32> @_inreg16xi32(i32 %a) {
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%b = insertelement <16 x i32> undef, i32 %a, i32 0
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%c = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer
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ret <16 x i32> %c
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}
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;CHECK-LABEL: _inreg8xi64:
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;CHECK: vpbroadcastq {{.*}}, %zmm
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;CHECK: ret
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define <8 x i64> @_inreg8xi64(i64 %a) {
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%b = insertelement <8 x i64> undef, i64 %a, i32 0
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%c = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
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ret <8 x i64> %c
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}
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;CHECK-LABEL: _inreg16xfloat:
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;CHECK: vbroadcastss {{.*}}, %zmm
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;CHECK: ret
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define <16 x float> @_inreg16xfloat(float %a) {
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%b = insertelement <16 x float> undef, float %a, i32 0
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%c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
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ret <16 x float> %c
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}
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;CHECK-LABEL: _inreg8xdouble:
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;CHECK: vbroadcastsd {{.*}}, %zmm
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;CHECK: ret
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define <8 x double> @_inreg8xdouble(double %a) {
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%b = insertelement <8 x double> undef, double %a, i32 0
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%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
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ret <8 x double> %c
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}
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;CHECK-LABEL: _xmm16xi32
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;CHECK: vpbroadcastd
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;CHECK: ret
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define <16 x i32> @_xmm16xi32(<16 x i32> %a) {
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%b = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> zeroinitializer
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ret <16 x i32> %b
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}
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;CHECK-LABEL: _xmm16xfloat
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;CHECK: vbroadcastss {{.*}}## encoding: [0x62
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;CHECK: ret
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define <16 x float> @_xmm16xfloat(<16 x float> %a) {
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%b = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> zeroinitializer
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ret <16 x float> %b
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}
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define <16 x i32> @test_vbroadcast() {
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; CHECK-LABEL: _test_vbroadcast:
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; CHECK: vpbroadcastd
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entry:
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%0 = sext <16 x i1> zeroinitializer to <16 x i32>
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%1 = fcmp uno <16 x float> undef, zeroinitializer
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%2 = sext <16 x i1> %1 to <16 x i32>
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%3 = select <16 x i1> %1, <16 x i32> %0, <16 x i32> %2
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ret <16 x i32> %3
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}
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