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b576c94c15
Header files will be on the way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9298 91177308-0d34-0410-b5e6-96231b3b80d8
134 lines
4.7 KiB
C++
134 lines
4.7 KiB
C++
//===-- PeepholeOptimizer.cpp - X86 Peephole Optimizer --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a peephole optimizer for the X86.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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namespace {
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struct PH : public MachineFunctionPass {
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virtual bool runOnMachineFunction(MachineFunction &MF);
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bool PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I);
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virtual const char *getPassName() const { return "X86 Peephole Optimizer"; }
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};
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}
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FunctionPass *createX86PeepholeOptimizerPass() { return new PH(); }
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bool PH::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
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for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
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if (PeepholeOptimize(*BI, I))
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Changed = true;
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else
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++I;
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return Changed;
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}
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bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I) {
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MachineInstr *MI = *I;
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MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
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unsigned Size = 0;
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switch (MI->getOpcode()) {
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case X86::MOVrr8:
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case X86::MOVrr16:
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case X86::MOVrr32: // Destroy X = X copies...
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if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
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I = MBB.erase(I);
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delete MI;
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return true;
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}
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return false;
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// A large number of X86 instructions have forms which take an 8-bit
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// immediate despite the fact that the operands are 16 or 32 bits. Because
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// this can save three bytes of code size (and icache space), we want to
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// shrink them if possible.
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case X86::ADDri16: case X86::ADDri32:
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case X86::SUBri16: case X86::SUBri32:
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case X86::IMULri16: case X86::IMULri32:
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case X86::ANDri16: case X86::ANDri32:
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case X86::ORri16: case X86::ORri32:
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case X86::XORri16: case X86::XORri32:
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assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
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if (MI->getOperand(2).isImmediate()) {
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int Val = MI->getOperand(2).getImmedValue();
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// If the value is the same when signed extended from 8 bits...
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if (Val == (signed int)(signed char)Val) {
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unsigned Opcode;
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switch (MI->getOpcode()) {
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default: assert(0 && "Unknown opcode value!");
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case X86::ADDri16: Opcode = X86::ADDri16b; break;
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case X86::ADDri32: Opcode = X86::ADDri32b; break;
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case X86::SUBri16: Opcode = X86::SUBri16b; break;
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case X86::SUBri32: Opcode = X86::SUBri32b; break;
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case X86::IMULri16: Opcode = X86::IMULri16b; break;
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case X86::IMULri32: Opcode = X86::IMULri32b; break;
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case X86::ANDri16: Opcode = X86::ANDri16b; break;
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case X86::ANDri32: Opcode = X86::ANDri32b; break;
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case X86::ORri16: Opcode = X86::ORri16b; break;
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case X86::ORri32: Opcode = X86::ORri32b; break;
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case X86::XORri16: Opcode = X86::XORri16b; break;
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case X86::XORri32: Opcode = X86::XORri32b; break;
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}
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unsigned R0 = MI->getOperand(0).getReg();
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unsigned R1 = MI->getOperand(1).getReg();
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*I = BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val);
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delete MI;
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return true;
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}
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}
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return false;
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#if 0
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case X86::MOVir32: Size++;
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case X86::MOVir16: Size++;
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case X86::MOVir8:
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// FIXME: We can only do this transformation if we know that flags are not
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// used here, because XOR clobbers the flags!
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if (MI->getOperand(1).isImmediate()) { // avoid mov EAX, <value>
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int Val = MI->getOperand(1).getImmedValue();
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if (Val == 0) { // mov EAX, 0 -> xor EAX, EAX
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static const unsigned Opcode[] ={X86::XORrr8,X86::XORrr16,X86::XORrr32};
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unsigned Reg = MI->getOperand(0).getReg();
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*I = BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg);
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delete MI;
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return true;
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} else if (Val == -1) { // mov EAX, -1 -> or EAX, -1
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// TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1'
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}
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}
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return false;
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#endif
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case X86::BSWAPr32: // Change bswap EAX, bswap EAX into nothing
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if (Next->getOpcode() == X86::BSWAPr32 &&
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MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) {
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I = MBB.erase(MBB.erase(I));
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delete MI;
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delete Next;
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return true;
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}
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return false;
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default:
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return false;
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}
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}
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