mirror of
https://github.com/c64scene-ar/llvm-6502.git
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75e818ad2f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100423 91177308-0d34-0410-b5e6-96231b3b80d8
366 lines
12 KiB
C++
366 lines
12 KiB
C++
//===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format MIPS assembly language.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-asm-printer"
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#include "Mips.h"
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#include "MipsSubtarget.h"
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#include "MipsInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "MipsMachineFunction.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Target/Mangler.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class MipsAsmPrinter : public AsmPrinter {
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const MipsSubtarget *Subtarget;
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public:
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explicit MipsAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
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: AsmPrinter(TM, Streamer) {
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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}
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virtual const char *getPassName() const {
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return "Mips Assembly Printer";
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}
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O);
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void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
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void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
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void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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const char *Modifier = 0);
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void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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const char *Modifier = 0);
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void printSavedRegsBitmask(raw_ostream &O);
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void printHex32(unsigned int Value, raw_ostream &O);
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const char *getCurrentABIString() const;
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void emitFrameDirective();
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void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd.
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void EmitInstruction(const MachineInstr *MI) {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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printInstruction(MI, OS);
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OutStreamer.EmitRawText(OS.str());
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}
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virtual void EmitFunctionBodyStart();
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virtual void EmitFunctionBodyEnd();
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static const char *getRegisterName(unsigned RegNo);
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virtual void EmitFunctionEntryLabel();
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void EmitStartOfAsmFile(Module &M);
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};
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} // end of anonymous namespace
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#include "MipsGenAsmWriter.inc"
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//===----------------------------------------------------------------------===//
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//
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// Mips Asm Directives
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//
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// -- Frame directive "frame Stackpointer, Stacksize, RARegister"
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// Describe the stack frame.
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//
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// -- Mask directives "(f)mask bitmask, offset"
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// Tells the assembler which registers are saved and where.
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// bitmask - contain a little endian bitset indicating which registers are
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// saved on function prologue (e.g. with a 0x80000000 mask, the
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// assembler knows the register 31 (RA) is saved at prologue.
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// offset - the position before stack pointer subtraction indicating where
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// the first saved register on prologue is located. (e.g. with a
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//
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// Consider the following function prologue:
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//
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// .frame $fp,48,$ra
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// .mask 0xc0000000,-8
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// addiu $sp, $sp, -48
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// sw $ra, 40($sp)
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// sw $fp, 36($sp)
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//
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// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
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// 30 (FP) are saved at prologue. As the save order on prologue is from
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// left to right, RA is saved first. A -8 offset means that after the
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// stack pointer subtration, the first register in the mask (RA) will be
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// saved at address 48-8=40.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Mask directives
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//===----------------------------------------------------------------------===//
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// Create a bitmask with all callee saved registers for CPU or Floating Point
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// registers. For CPU registers consider RA, GP and FP for saving if necessary.
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void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
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const TargetRegisterInfo &RI = *TM.getRegisterInfo();
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const MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
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// CPU and FPU Saved Registers Bitmasks
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unsigned int CPUBitmask = 0;
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unsigned int FPUBitmask = 0;
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// Set the CPU and FPU Bitmasks
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const MachineFrameInfo *MFI = MF->getFrameInfo();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(CSI[i].getReg());
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if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
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CPUBitmask |= (1 << RegNum);
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else
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FPUBitmask |= (1 << RegNum);
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}
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// Return Address and Frame registers must also be set in CPUBitmask.
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if (RI.hasFP(*MF))
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CPUBitmask |= (1 << MipsRegisterInfo::
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getRegisterNumbering(RI.getFrameRegister(*MF)));
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if (MFI->hasCalls())
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CPUBitmask |= (1 << MipsRegisterInfo::
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getRegisterNumbering(RI.getRARegister()));
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// Print CPUBitmask
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O << "\t.mask \t"; printHex32(CPUBitmask, O);
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O << ',' << MipsFI->getCPUTopSavedRegOff() << '\n';
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// Print FPUBitmask
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O << "\t.fmask\t"; printHex32(FPUBitmask, O); O << ","
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<< MipsFI->getFPUTopSavedRegOff() << '\n';
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}
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// Print a 32 bit hex number with all numbers.
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void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
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O << "0x";
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for (int i = 7; i >= 0; i--)
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O << utohexstr((Value & (0xF << (i*4))) >> (i*4));
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}
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//===----------------------------------------------------------------------===//
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// Frame and Set directives
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//===----------------------------------------------------------------------===//
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/// Frame Directive
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void MipsAsmPrinter::emitFrameDirective() {
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const TargetRegisterInfo &RI = *TM.getRegisterInfo();
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unsigned stackReg = RI.getFrameRegister(*MF);
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unsigned returnReg = RI.getRARegister();
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unsigned stackSize = MF->getFrameInfo()->getStackSize();
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OutStreamer.EmitRawText("\t.frame\t$" +
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Twine(LowercaseString(getRegisterName(stackReg))) +
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"," + Twine(stackSize) + ",$" +
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Twine(LowercaseString(getRegisterName(returnReg))));
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}
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/// Emit Set directives.
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const char *MipsAsmPrinter::getCurrentABIString() const {
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switch (Subtarget->getTargetABI()) {
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case MipsSubtarget::O32: return "abi32";
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case MipsSubtarget::O64: return "abiO64";
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case MipsSubtarget::N32: return "abiN32";
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case MipsSubtarget::N64: return "abi64";
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case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
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default: break;
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}
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llvm_unreachable("Unknown Mips ABI");
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return NULL;
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}
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void MipsAsmPrinter::EmitFunctionEntryLabel() {
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OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
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OutStreamer.EmitLabel(CurrentFnSym);
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}
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/// EmitFunctionBodyStart - Targets can override this to emit stuff before
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/// the first basic block in the function.
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void MipsAsmPrinter::EmitFunctionBodyStart() {
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emitFrameDirective();
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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printSavedRegsBitmask(OS);
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OutStreamer.EmitRawText(OS.str());
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}
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/// EmitFunctionBodyEnd - Targets can override this to emit stuff after
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/// the last basic block in the function.
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void MipsAsmPrinter::EmitFunctionBodyEnd() {
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// There are instruction for this macros, but they must
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// always be at the function end, and we can't emit and
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// break with BB logic.
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OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
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OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
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OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
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}
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// Print out an operand for an inline asm expression.
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bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant,const char *ExtraCode,
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raw_ostream &O) {
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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printOperand(MI, OpNo, O);
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return false;
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}
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void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(opNum);
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bool closeP = false;
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if (MO.getTargetFlags())
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closeP = true;
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switch(MO.getTargetFlags()) {
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case MipsII::MO_GPREL: O << "%gp_rel("; break;
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case MipsII::MO_GOT_CALL: O << "%call16("; break;
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case MipsII::MO_GOT:
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if (MI->getOpcode() == Mips::LW)
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O << "%got(";
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else
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O << "%lo(";
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break;
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case MipsII::MO_ABS_HILO:
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if (MI->getOpcode() == Mips::LUi)
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O << "%hi(";
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else
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O << "%lo(";
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break;
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}
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switch (MO.getType()) {
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case MachineOperand::MO_Register:
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O << '$' << LowercaseString(getRegisterName(MO.getReg()));
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break;
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case MachineOperand::MO_Immediate:
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O << (short int)MO.getImm();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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O << *MO.getMBB()->getSymbol();
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return;
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case MachineOperand::MO_GlobalAddress:
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O << *Mang->getSymbol(MO.getGlobal());
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break;
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case MachineOperand::MO_ExternalSymbol:
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O << *GetExternalSymbolSymbol(MO.getSymbolName());
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break;
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case MachineOperand::MO_JumpTableIndex:
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O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
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<< '_' << MO.getIndex();
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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O << MAI->getPrivateGlobalPrefix() << "CPI"
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<< getFunctionNumber() << "_" << MO.getIndex();
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if (MO.getOffset())
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O << "+" << MO.getOffset();
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break;
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default:
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llvm_unreachable("<unknown operand type>");
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}
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if (closeP) O << ")";
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}
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void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
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raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(opNum);
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if (MO.getType() == MachineOperand::MO_Immediate)
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O << (unsigned short int)MO.getImm();
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else
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printOperand(MI, opNum, O);
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}
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void MipsAsmPrinter::
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printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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const char *Modifier) {
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// when using stack locations for not load/store instructions
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// print the same way as all normal 3 operand instructions.
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if (Modifier && !strcmp(Modifier, "stackloc")) {
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printOperand(MI, opNum+1, O);
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O << ", ";
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printOperand(MI, opNum, O);
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return;
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}
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// Load/Store memory operands -- imm($reg)
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// If PIC target the target is loaded as the
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// pattern lw $25,%call16($28)
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printOperand(MI, opNum, O);
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O << "(";
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printOperand(MI, opNum+1, O);
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O << ")";
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}
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void MipsAsmPrinter::
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printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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const char *Modifier) {
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const MachineOperand& MO = MI->getOperand(opNum);
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O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
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}
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void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
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// FIXME: Use SwitchSection.
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// Tell the assembler which ABI we are using
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OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
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// TODO: handle O64 ABI
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if (Subtarget->isABI_EABI()) {
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if (Subtarget->isGP32bit())
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OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
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else
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OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
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}
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// return to previous section
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OutStreamer.EmitRawText(StringRef("\t.previous"));
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}
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// Force static initialization.
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extern "C" void LLVMInitializeMipsAsmPrinter() {
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RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
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RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
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}
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