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const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
200 lines
7.4 KiB
C++
200 lines
7.4 KiB
C++
//===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that XCore uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef XCOREISELLOWERING_H
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#define XCOREISELLOWERING_H
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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#include "XCore.h"
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namespace llvm {
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// Forward delcarations
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class XCoreSubtarget;
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class XCoreTargetMachine;
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namespace XCoreISD {
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enum NodeType {
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// Start the numbering where the builtin ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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// Branch and link (call)
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BL,
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// pc relative address
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PCRelativeWrapper,
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// dp relative address
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DPRelativeWrapper,
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// cp relative address
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CPRelativeWrapper,
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// Store word to stack
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STWSP,
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// Corresponds to retsp instruction
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RETSP,
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// Corresponds to LADD instruction
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LADD,
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// Corresponds to LSUB instruction
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LSUB,
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// Corresponds to LMUL instruction
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LMUL,
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// Corresponds to MACCU instruction
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MACCU,
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// Corresponds to MACCS instruction
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MACCS,
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// Jumptable branch.
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BR_JT,
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// Jumptable branch using long branches for each entry.
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BR_JT32
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};
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class XCoreTargetLowering : public TargetLowering
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{
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public:
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explicit XCoreTargetLowering(XCoreTargetMachine &TM);
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virtual unsigned getJumpTableEncoding() const;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/// ReplaceNodeResults - Replace the results of node with an illegal result
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/// type with new values built out of custom code.
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///
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virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const;
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/// getTargetNodeName - This method returns the name of a target specific
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// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
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virtual bool isLegalAddressingMode(const AddrMode &AM,
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const Type *Ty) const;
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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virtual unsigned getFunctionAlignment(const Function *F) const;
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private:
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const XCoreTargetMachine &TM;
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const XCoreSubtarget &Subtarget;
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// Lower Operand helpers
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SDValue LowerCCCArguments(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
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SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
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SelectionDAG &DAG) const;
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// Lower Operand specifics
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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// Inline asm support
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const;
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// Expand specifics
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SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
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SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual void computeMaskedBitsForTargetNode(const SDValue Op,
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const APInt &Mask,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerCall(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool &isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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DebugLoc dl, SelectionDAG &DAG) const;
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virtual bool
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CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<EVT> &OutTys,
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const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
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SelectionDAG &DAG) const;
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};
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}
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#endif // XCOREISELLOWERING_H
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