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compute the maximum element directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56411 91177308-0d34-0410-b5e6-96231b3b80d8
99 lines
3.7 KiB
C++
99 lines
3.7 KiB
C++
//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetRegisterInfo interface.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/ADT/BitVector.h"
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using namespace llvm;
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TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
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regclass_iterator RCB, regclass_iterator RCE,
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int CFSO, int CFDO,
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const unsigned* subregs, const unsigned subregsize)
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: SubregHash(subregs), SubregHashSize(subregsize), Desc(D), NumRegs(NR),
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RegClassBegin(RCB), RegClassEnd(RCE) {
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assert(NumRegs < FirstVirtualRegister &&
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"Target has too many physical registers!");
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CallFrameSetupOpcode = CFSO;
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CallFrameDestroyOpcode = CFDO;
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}
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TargetRegisterInfo::~TargetRegisterInfo() {}
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/// getPhysicalRegisterRegClass - Returns the Register Class of a physical
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/// register of the given type. If type is MVT::Other, then just return any
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/// register class the register belongs to.
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const TargetRegisterClass *
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TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const {
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assert(isPhysicalRegister(reg) && "reg must be a physical register");
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// Pick the most super register class of the right type that contains
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// this physreg.
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const TargetRegisterClass* BestRC = 0;
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for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
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const TargetRegisterClass* RC = *I;
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if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
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(!BestRC || BestRC->hasSuperClass(RC)))
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BestRC = RC;
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}
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assert(BestRC && "Couldn't find the register class");
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return BestRC;
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}
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/// getAllocatableSetForRC - Toggle the bits that represent allocatable
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/// registers for the specific register class.
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static void getAllocatableSetForRC(MachineFunction &MF,
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const TargetRegisterClass *RC, BitVector &R){
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for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
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E = RC->allocation_order_end(MF); I != E; ++I)
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R.set(*I);
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}
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BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF,
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const TargetRegisterClass *RC) const {
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BitVector Allocatable(NumRegs);
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if (RC) {
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getAllocatableSetForRC(MF, RC, Allocatable);
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return Allocatable;
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}
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for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
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E = regclass_end(); I != E; ++I)
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getAllocatableSetForRC(MF, *I, Allocatable);
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return Allocatable;
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}
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/// getFrameIndexOffset - Returns the displacement from the frame register to
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/// the stack frame of the specified index. This is the default implementation
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/// which is likely incorrect for the target.
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int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
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const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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return MFI->getObjectOffset(FI) + MFI->getStackSize() -
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TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
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}
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/// getInitialFrameState - Returns a list of machine moves that are assumed
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/// on entry to a function.
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void
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TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
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// Default is to do nothing.
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}
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