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absaddr-store.ll
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Hexagon: Use multiclass for absolute addressing mode stores.
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2013-02-05 18:15:34 +00:00 |
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adde.ll
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Hexagon: Expand addc, adde, subc and sube.
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2013-03-05 19:04:47 +00:00 |
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args.ll
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Hexagon: Add encoding bits to the TFR64 instructions.
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2013-03-05 18:42:28 +00:00 |
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block-addr.ll
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Hexagon: Add support to lower block address.
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2013-03-07 19:10:28 +00:00 |
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cext-check.ll
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Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.
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2013-02-20 16:13:27 +00:00 |
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cext-valid-packet1.ll
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Hexagon: Add constant extender support framework.
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2013-03-01 17:37:13 +00:00 |
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cext-valid-packet2.ll
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Hexagon: Add constant extender support framework.
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2013-03-01 17:37:13 +00:00 |
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cmp_pred_reg.ll
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Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle
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2013-02-05 19:20:45 +00:00 |
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cmp_pred.ll
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Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle
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2013-02-05 19:20:45 +00:00 |
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cmp-to-genreg.ll
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Hexagon: Add V4 compare instructions. Enable relationship mapping
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2013-02-05 16:42:24 +00:00 |
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cmp-to-predreg.ll
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Hexagon: Add V4 compare instructions. Enable relationship mapping
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2013-02-05 16:42:24 +00:00 |
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cmpb_pred.ll
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Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle
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2013-02-05 19:20:45 +00:00 |
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combine_ir.ll
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Hexagon: Add V4 combine instructions and some more Def Pats for V2.
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2013-02-04 15:52:56 +00:00 |
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combine.ll
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convertdptoint.ll
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convertdptoll.ll
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convertsptoint.ll
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convertsptoll.ll
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ctlz-cttz-ctpop.ll
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Hexagon: Expand cttz, ctlz, and ctpop for now.
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2013-02-21 19:39:40 +00:00 |
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dadd.ll
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dmul.ll
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double.ll
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doubleconvert-ieee-rnd-near.ll
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dsub.ll
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dualstore.ll
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Hexagon: Add encoding bits to the TFR64 instructions.
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2013-03-05 18:42:28 +00:00 |
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fadd.ll
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fcmp.ll
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float.ll
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floatconvert-ieee-rnd-near.ll
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fmul.ll
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frame.ll
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fsub.ll
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fusedandshift.ll
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gp-plus-offset-load.ll
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Hexagon: Use absolute addressing mode loads/stores for global+offset
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2013-02-13 21:38:46 +00:00 |
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gp-plus-offset-store.ll
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Hexagon: Use absolute addressing mode loads/stores for global+offset
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2013-02-13 21:38:46 +00:00 |
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hwloop-cleanup.ll
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Extend Hexagon hardware loop generation to handle various additional cases:
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2013-02-11 21:37:55 +00:00 |
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hwloop-const.ll
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Extend Hexagon hardware loop generation to handle various additional cases:
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2013-02-11 21:37:55 +00:00 |
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hwloop-dbg.ll
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Extend Hexagon hardware loop generation to handle various additional cases:
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2013-02-11 21:37:55 +00:00 |
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hwloop-le.ll
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Extend Hexagon hardware loop generation to handle various additional cases:
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2013-02-11 21:37:55 +00:00 |
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hwloop-lt1.ll
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Extend Hexagon hardware loop generation to handle various additional cases:
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2013-02-11 21:37:55 +00:00 |
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hwloop-lt.ll
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Extend Hexagon hardware loop generation to handle various additional cases:
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2013-02-11 21:37:55 +00:00 |
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hwloop-ne.ll
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Extend Hexagon hardware loop generation to handle various additional cases:
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2013-02-11 21:37:55 +00:00 |
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i1_VarArg.ll
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Hexagon: Handle i8, i16 and i1 Var Args.
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2013-03-07 20:28:34 +00:00 |
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i8_VarArg.ll
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Hexagon: Handle i8, i16 and i1 Var Args.
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2013-03-07 20:28:34 +00:00 |
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i16_VarArg.ll
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Hexagon: Handle i8, i16 and i1 Var Args.
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2013-03-07 20:28:34 +00:00 |
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idxload-with-zero-offset.ll
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Hexagon: Test case to confirm generation of indexed loads with zero offset.
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2013-02-01 16:40:06 +00:00 |
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indirect-br.ll
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Hexagon: Add support to lower block address.
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2013-03-07 19:10:28 +00:00 |
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lit.local.cfg
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macint.ll
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mpy.ll
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newvaluejump2.ll
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newvaluejump.ll
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newvaluestore.ll
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opt-fabs.ll
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opt-fneg.ll
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postinc-load.ll
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In hexagon convertToHardwareLoop, don't deref end() iterator
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2012-12-07 21:03:15 +00:00 |
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postinc-store.ll
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Hexagon: Add testcase for post-increment store instructions.
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2013-02-05 18:23:51 +00:00 |
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pred-absolute-store.ll
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Hexagon: Add support to generate predicated absolute addressing mode
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2013-02-12 16:06:23 +00:00 |
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predicate-copy.ll
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Hexagon: add support for predicate-GPR copies.
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2013-02-13 22:56:34 +00:00 |
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remove_lsr.ll
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simpletailcall.ll
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static.ll
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struct_args_large.ll
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struct_args.ll
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Hexagon: Add V4 combine instructions and some more Def Pats for V2.
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2013-02-04 15:52:56 +00:00 |
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sube.ll
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Hexagon: Expand addc, adde, subc and sube.
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2013-03-05 19:04:47 +00:00 |
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vaddh.ll
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validate-offset.ll
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Add indexed load/store instructions for offset validation check.
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2013-01-17 18:42:37 +00:00 |
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zextloadi1.ll
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Hexagon: Add patterns for zero extended loads from i1->i64.
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2013-03-08 14:15:15 +00:00 |
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