Geoff Berry 0dd663b598 [AArch64] Favor extended reg patterns for sub ... Summary: Favor the extended reg patterns over the shifted reg patterns that match only the operand shift and not the full sign/zero extend and shift. Reviewers: jmolloy, t.p.northover Subscribers: mcrosier, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11569 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243753 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-31 15:55:54 +00:00
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Analysis	[X86][SSE] Vectorize i64 ASHR operations	2015-07-29 20:31:45 +00:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen	[AArch64] Favor extended reg patterns for sub	2015-07-31 15:55:54 +00:00
DebugInfo	[mips] Fix out-of-date debug information in test file.	2015-07-30 13:13:09 +00:00
ExecutionEngine
Feature
FileCheck
Instrumentation	[libFuzzer] trace switch statements and apply mutations based on the expected case values	2015-07-31 01:33:06 +00:00
Integer
JitListener
LibDriver
Linker
LTO
MC
Object	ELFYAML: Enable parsing of EM_AMDGPU	2015-07-31 01:15:15 +00:00
Other
SymbolRewriter
TableGen	TableGen: Support folding casts from bits to int	2015-07-31 01:12:06 +00:00
tools	[dsymutil] Rename -v option to -verbose	2015-07-29 22:29:34 +00:00
Transforms	[SLP vectorizer]: Choose the best consecutive candidate to pair with a store instruction.	2015-07-30 17:40:39 +00:00
Unit
Verifier	[Statepoints] Let patchable statepoints have a symbolic call target.	2015-07-28 23:50:30 +00:00
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
TestRunner.sh