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4a74b3b933
Coalescing can remove copy-like instructions with sub-register operands that constrained the register class. Examples are: x86: GR32_ABCD:sub_8bit_hi -> GR32 arm: DPR_VFP2:ssub0 -> DPR Recompute the register class of any virtual registers that are used by less instructions after coalescing. This affects code generation for the Cortex-A8 where we use NEON instructions for f32 operations, c.f. fp_convert.ll: vadd.f32 d16, d1, d0 vcvt.s32.f32 d0, d16 The register allocator is now free to use d16 for the temporary, and that comes first in the allocation order because it doesn't interfere with any s-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137133 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
798 B
LLVM
30 lines
798 B
LLVM
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
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; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
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define float @test(float %a, float %b) {
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entry:
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%dum = fadd float %a, %b
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%0 = tail call float @fabsf(float %dum)
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%dum1 = fadd float %0, %b
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ret float %dum1
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}
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declare float @fabsf(float)
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; VFP2: test:
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; VFP2: vabs.f32 s1, s1
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; NFP1: test:
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; NFP1: vabs.f32 d1, d1
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; NFP0: test:
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; NFP0: vabs.f32 s1, s1
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; CORTEXA8: test:
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; CORTEXA8: vadd.f32 [[D1:d[0-9]+]]
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; CORTEXA8: vabs.f32 {{d[0-9]+}}, [[D1]]
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; CORTEXA9: test:
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; CORTEXA9: vabs.f32 s{{.}}, s{{.}}
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