Matthias Braun 0dec0e1ea5 ARM: Add scheduling information for LDRLIT instructions to swift scheduling model ... These pseudo instructions are only lowered after register allocation and are therefore still present when the machine scheduler runs. Add a run: line to a testcase that uses the uncommon flags necessary to actually produce a LDRLIT instruction on swift. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242587 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-17 23:18:26 +00:00
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AArch64	[RAGreedy] Add an experimental deferred spilling feature.	2015-07-17 23:04:06 +00:00
AMDGPU	Only do fmul (fadd x, x), c combine if the fadd only has one use	2015-07-17 01:14:35 +00:00
ARM	Revert "ARM: Enable MachineScheduler and disable PostRAScheduler for swift."	2015-07-17 18:14:19 +00:00
BPF
CPP
Generic
Hexagon	[Hexagon] Generate instructions for operations on predicate registers	2015-07-14 19:30:21 +00:00
Inputs
Mips	[SDAG] Optimize unordered comparison in soft-float mode (patch by Anton Nadolskiy)	2015-07-15 08:39:35 +00:00
MIR	MIR Parser: Allow the dollar characters in all of the identifier tokens.	2015-07-17 22:48:04 +00:00
MSP430
NVPTX	Use inbounds GEPs for memcpy and memset lowering	2015-07-17 16:42:33 +00:00
PowerPC	[PowerPC] v4i32 is a VSRCRegClass	2015-07-16 21:14:07 +00:00
SPARC	[SPARC] Cleanup handling of the Y/ASR registers.	2015-07-08 16:25:12 +00:00
SystemZ
Thumb
Thumb2	ARM: Add scheduling information for LDRLIT instructions to swift scheduling model	2015-07-17 23:18:26 +00:00
WebAssembly
WinEH	[WinEH] Strip the \01 character from the __CxxFrameHandler3 thunk name	2015-07-13 17:55:14 +00:00
X86	Use small encodings for constants when possible.	2015-07-17 00:57:52 +00:00
XCore