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1. If we are two-addressing a commutable instruction and the LHS is not the last use of the variable, see if the instruction is the last use of the RHS. If so, commute the instruction, allowing us to avoid a register-register copy in many cases for common instructions like ADD, OR, AND, etc on X86. 2. If #1 doesn't hold, and if this is an instruction that also existing in 3-address form, promote the instruction to a 3-address instruction to avoid the register-register copy. We can do this for several common instructions in X86, including ADDrr, INC, DEC, etc. This patch implements test/Regression/CodeGen/X86/commute-two-addr.ll, overlap-add.ll, and overlap-shift.ll when I check in the X86 support for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19245 91177308-0d34-0410-b5e6-96231b3b80d8
206 lines
7.8 KiB
C++
206 lines
7.8 KiB
C++
//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TwoAddress instruction pass which is used
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// by most register allocators. Two-Address instructions are rewritten
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// from:
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//
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// A = B op C
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//
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// to:
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//
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// A = B
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// A op= C
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//
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// Note that if a register allocator chooses to use this pass, that it
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// has to be capable of handling the non-SSA nature of these rewritten
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// virtual registers.
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//
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// It is also worth noting that the duplicate operand of the two
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// address instruction is removed.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "twoaddrinstr"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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namespace {
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Statistic<> NumTwoAddressInstrs("twoaddressinstruction",
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"Number of two-address instructions");
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Statistic<> NumCommuted("twoaddressinstruction",
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"Number of instructions commuted to coallesce");
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Statistic<> NumConvertedTo3Addr("twoaddressinstruction",
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"Number of instructions promoted to 3-address");
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struct TwoAddressInstructionPass : public MachineFunctionPass {
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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/// runOnMachineFunction - pass entry point
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bool runOnMachineFunction(MachineFunction&);
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};
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RegisterPass<TwoAddressInstructionPass>
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X("twoaddressinstruction", "Two-Address instruction pass");
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};
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const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
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void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LiveVariables>();
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AU.addPreserved<LiveVariables>();
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AU.addPreservedID(PHIEliminationID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - Reduce two-address instructions to two
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/// operands.
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///
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bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(std::cerr << "Machine Function\n");
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo &MRI = *TM.getRegisterInfo();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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LiveVariables &LV = getAnalysis<LiveVariables>();
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bool MadeChange = false;
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DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n");
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DEBUG(std::cerr << "********** Function: "
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<< MF.getFunction()->getName() << '\n');
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for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
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mbbi != mbbe; ++mbbi) {
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for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
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mi != me; ++mi) {
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unsigned opcode = mi->getOpcode();
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// ignore if it is not a two-address instruction
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if (!TII.isTwoAddrInstr(opcode))
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continue;
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++NumTwoAddressInstrs;
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DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
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assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() &&
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mi->getOperand(1).isUse() && "two address instruction invalid");
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// if the two operands are the same we just remove the use
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// and mark the def as def&use, otherwise we have to insert a copy.
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if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) {
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// rewrite:
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// a = b op c
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// to:
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// a = b
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// a = a op c
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unsigned regA = mi->getOperand(0).getReg();
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unsigned regB = mi->getOperand(1).getReg();
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assert(MRegisterInfo::isVirtualRegister(regA) &&
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MRegisterInfo::isVirtualRegister(regB) &&
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"cannot update physical register live information");
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#ifndef NDEBUG
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// First, verify that we do not have a use of a in the instruction (a =
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// b + a for example) because our transformation will not work. This
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// should never occur because we are in SSA form.
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for (unsigned i = 1; i != mi->getNumOperands(); ++i)
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assert(!mi->getOperand(i).isRegister() ||
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mi->getOperand(i).getReg() != regA);
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#endif
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// If this instruction is not the killing user of B, see if we can
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// rearrange the code to make it so. Making it the killing user will
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// allow us to coallesce A and B together, eliminating the copy we are
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// about to insert.
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if (!LV.KillsRegister(mi, regB)) {
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const TargetInstrDescriptor &TID = TII.get(opcode);
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// If this instruction is commutative, check to see if C dies. If so,
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// swap the B and C operands. This makes the live ranges of A and C
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// joinable.
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if (TID.Flags & M_COMMUTABLE) {
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assert(mi->getOperand(2).isRegister() &&
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"Not a proper commutative instruction!");
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unsigned regC = mi->getOperand(2).getReg();
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if (LV.KillsRegister(mi, regC)) {
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DEBUG(std::cerr << "2addr: COMMUTING : " << *mi);
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mi->SetMachineOperandReg(2, regB);
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mi->SetMachineOperandReg(1, regC);
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DEBUG(std::cerr << "2addr: COMMUTED TO: " << *mi);
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++NumCommuted;
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regB = regC;
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goto InstructionRearranged;
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}
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}
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// If this instruction is potentially convertible to a true
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// three-address instruction,
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if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
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if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
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DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi);
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DEBUG(std::cerr << "2addr: TO 3-ADDR: " << *New);
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LV.instructionChanged(mi, New); // Update live variables
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mbbi->insert(mi, New); // Insert the new inst
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mbbi->erase(mi); // Nuke the old inst.
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mi = New;
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++NumConvertedTo3Addr;
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assert(!TII.isTwoAddrInstr(New->getOpcode()) &&
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"convertToThreeAddress returned a 2-addr instruction??");
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// Done with this instruction.
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continue;
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}
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}
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InstructionRearranged:
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const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
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MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
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MachineBasicBlock::iterator prevMi = prior(mi);
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DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
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// Update live variables for regA
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LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
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varInfo.DefInst = prevMi;
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// update live variables for regB
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if (LV.removeVirtualRegisterKilled(regB, mbbi, mi))
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LV.addVirtualRegisterKilled(regB, prevMi);
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if (LV.removeVirtualRegisterDead(regB, mbbi, mi))
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LV.addVirtualRegisterDead(regB, prevMi);
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// replace all occurences of regB with regA
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for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
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if (mi->getOperand(i).isRegister() &&
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mi->getOperand(i).getReg() == regB)
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mi->SetMachineOperandReg(i, regA);
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}
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}
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assert(mi->getOperand(0).isDef());
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mi->getOperand(0).setUse();
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mi->RemoveOperand(1);
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MadeChange = true;
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DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));
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}
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}
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return MadeChange;
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}
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