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Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
255 lines
7.7 KiB
C++
255 lines
7.7 KiB
C++
//===-- DelaySlotFiller.cpp - MBlaze delay slot filler --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// A pass that attempts to fill instructions with delay slots. If no
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// instructions can be moved into the delay slot then a NOP is placed there.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "delay-slot-filler"
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#include "MBlaze.h"
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#include "MBlazeTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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STATISTIC(FilledSlots, "Number of delay slots filled");
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static cl::opt<bool> MBDisableDelaySlotFiller(
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"disable-mblaze-delay-filler",
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cl::init(false),
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cl::desc("Disable the MBlaze delay slot filter."),
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cl::Hidden);
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namespace {
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struct Filler : public MachineFunctionPass {
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TargetMachine &TM;
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const TargetInstrInfo *TII;
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static char ID;
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Filler(TargetMachine &tm)
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: MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
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virtual const char *getPassName() const {
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return "MBlaze Delay Slot Filler";
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}
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bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F) {
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bool Changed = false;
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for (MachineFunction::iterator FI = F.begin(), FE = F.end();
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FI != FE; ++FI)
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Changed |= runOnMachineBasicBlock(*FI);
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return Changed;
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}
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};
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char Filler::ID = 0;
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} // end of anonymous namespace
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static bool hasImmInstruction(MachineBasicBlock::iterator &candidate) {
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// Any instruction with an immediate mode operand greater than
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// 16-bits requires an implicit IMM instruction.
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unsigned numOper = candidate->getNumOperands();
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for (unsigned op = 0; op < numOper; ++op) {
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MachineOperand &mop = candidate->getOperand(op);
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// The operand requires more than 16-bits to represent.
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if (mop.isImm() && (mop.getImm() < -0x8000 || mop.getImm() > 0x7fff))
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return true;
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// We must assume that unknown immediate values require more than
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// 16-bits to represent.
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if (mop.isGlobal() || mop.isSymbol() || mop.isJTI() || mop.isCPI())
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return true;
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// FIXME: we could probably check to see if the FP value happens
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// to not need an IMM instruction. For now we just always
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// assume that FP values do.
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if (mop.isFPImm())
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return true;
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}
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return false;
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}
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static unsigned getLastRealOperand(MachineBasicBlock::iterator &instr) {
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switch (instr->getOpcode()) {
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default: return instr->getNumOperands();
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// These instructions have a variable number of operands but the first two
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// are the "real" operands that we care about during hazard detection.
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case MBlaze::BRLID:
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case MBlaze::BRALID:
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case MBlaze::BRLD:
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case MBlaze::BRALD:
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return 2;
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}
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}
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static bool delayHasHazard(MachineBasicBlock::iterator &candidate,
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MachineBasicBlock::iterator &slot) {
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// Hazard check
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MachineBasicBlock::iterator a = candidate;
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MachineBasicBlock::iterator b = slot;
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// MBB layout:-
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// candidate := a0 = operation(a1, a2)
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// ...middle bit...
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// slot := b0 = operation(b1, b2)
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// Possible hazards:-/
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// 1. a1 or a2 was written during the middle bit
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// 2. a0 was read or written during the middle bit
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// 3. a0 is one or more of {b0, b1, b2}
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// 4. b0 is one or more of {a1, a2}
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// 5. a accesses memory, and the middle bit
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// contains a store operation.
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bool a_is_memory = candidate->mayLoad() || candidate->mayStore();
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// Determine the number of operands in the slot instruction and in the
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// candidate instruction.
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const unsigned aend = getLastRealOperand(a);
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const unsigned bend = getLastRealOperand(b);
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// Check hazards type 1, 2 and 5 by scanning the middle bit
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MachineBasicBlock::iterator m = a;
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for (++m; m != b; ++m) {
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for (unsigned aop = 0; aop<aend; ++aop) {
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bool aop_is_reg = a->getOperand(aop).isReg();
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if (!aop_is_reg) continue;
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bool aop_is_def = a->getOperand(aop).isDef();
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unsigned aop_reg = a->getOperand(aop).getReg();
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const unsigned mend = getLastRealOperand(m);
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for (unsigned mop = 0; mop<mend; ++mop) {
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bool mop_is_reg = m->getOperand(mop).isReg();
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if (!mop_is_reg) continue;
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bool mop_is_def = m->getOperand(mop).isDef();
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unsigned mop_reg = m->getOperand(mop).getReg();
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if (aop_is_def && (mop_reg == aop_reg))
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return true; // Hazard type 2, because aop = a0
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else if (mop_is_def && (mop_reg == aop_reg))
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return true; // Hazard type 1, because aop in {a1, a2}
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}
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}
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// Check hazard type 5
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if (a_is_memory && m->mayStore())
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return true;
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}
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// Check hazard type 3 & 4
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for (unsigned aop = 0; aop<aend; ++aop) {
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if (a->getOperand(aop).isReg()) {
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unsigned aop_reg = a->getOperand(aop).getReg();
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for (unsigned bop = 0; bop<bend; ++bop) {
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if (b->getOperand(bop).isReg() && !b->getOperand(bop).isImplicit()) {
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unsigned bop_reg = b->getOperand(bop).getReg();
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if (aop_reg == bop_reg)
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return true;
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}
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}
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}
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}
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return false;
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}
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static bool isDelayFiller(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator candidate) {
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if (candidate == MBB.begin())
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return false;
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--candidate;
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return (candidate->hasDelaySlot());
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}
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static bool hasUnknownSideEffects(MachineBasicBlock::iterator &I) {
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if (!I->hasUnmodeledSideEffects())
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return false;
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unsigned op = I->getOpcode();
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if (op == MBlaze::ADDK || op == MBlaze::ADDIK ||
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op == MBlaze::ADDC || op == MBlaze::ADDIC ||
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op == MBlaze::ADDKC || op == MBlaze::ADDIKC ||
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op == MBlaze::RSUBK || op == MBlaze::RSUBIK ||
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op == MBlaze::RSUBC || op == MBlaze::RSUBIC ||
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op == MBlaze::RSUBKC || op == MBlaze::RSUBIKC)
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return false;
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return true;
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}
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static MachineBasicBlock::iterator
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findDelayInstr(MachineBasicBlock &MBB,MachineBasicBlock::iterator slot) {
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MachineBasicBlock::iterator I = slot;
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while (true) {
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if (I == MBB.begin())
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break;
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--I;
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if (I->hasDelaySlot() || I->isBranch() || isDelayFiller(MBB,I) ||
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I->isCall() || I->isReturn() || I->isBarrier() ||
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hasUnknownSideEffects(I))
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break;
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if (hasImmInstruction(I) || delayHasHazard(I,slot))
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continue;
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return I;
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}
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return MBB.end();
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}
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/// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
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/// Currently, we fill delay slots with NOPs. We assume there is only one
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/// delay slot per delayed instruction.
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bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
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if (I->hasDelaySlot()) {
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MachineBasicBlock::iterator D = MBB.end();
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MachineBasicBlock::iterator J = I;
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if (!MBDisableDelaySlotFiller)
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D = findDelayInstr(MBB,I);
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++FilledSlots;
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Changed = true;
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if (D == MBB.end())
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BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(MBlaze::NOP));
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else
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MBB.splice(++J, &MBB, D);
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}
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return Changed;
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}
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/// createMBlazeDelaySlotFillerPass - Returns a pass that fills in delay
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/// slots in MBlaze MachineFunctions
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FunctionPass *llvm::createMBlazeDelaySlotFillerPass(MBlazeTargetMachine &tm) {
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return new Filler(tm);
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}
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