mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 17:29:19 +00:00
Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223113 91177308-0d34-0410-b5e6-96231b3b80d8
704 lines
28 KiB
ArmAsm
704 lines
28 KiB
ArmAsm
@ RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
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@ RUN: not llvm-mc -triple=armv8 < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V8 < %t %s
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@ Check for various assembly diagnostic messages on invalid input.
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@ 's' bit on an instruction that can't accept it.
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mlss r1, r2, r3, r4
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@ CHECK-ERRORS: error: instruction 'mls' can not set flags,
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@ CHECK-ERRORS: but 's' suffix specified
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@ Out of range shift immediate values.
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adc r1, r2, r3, lsl #invalid
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adc r4, r5, r6, lsl #-1
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adc r4, r5, r6, lsl #32
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adc r4, r5, r6, lsr #-1
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adc r4, r5, r6, lsr #33
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adc r4, r5, r6, asr #-1
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adc r4, r5, r6, asr #33
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adc r4, r5, r6, ror #-1
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adc r4, r5, r6, ror #32
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@ CHECK-ERRORS: error: invalid immediate shift value
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@ CHECK-ERRORS: adc r1, r2, r3, lsl #invalid
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, lsl #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, lsl #32
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, lsr #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, lsr #33
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, asr #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, asr #33
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, ror #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, ror #32
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@ Out of range shift immediate values for load/store.
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str r1, [r2, r3, lsl #invalid]
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ldr r4, [r5], r6, lsl #-1
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pld r4, [r5, r6, lsl #32]
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str r4, [r5], r6, lsr #-1
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ldr r4, [r5, r6, lsr #33]
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pld r4, [r5, r6, asr #-1]
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str r4, [r5, r6, asr #33]
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ldr r4, [r5, r6, ror #-1]
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pld r4, [r5, r6, ror #32]
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pld r4, [r5, r6, rrx #0]
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@ CHECK-ERRORS: error: shift amount must be an immediate
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@ CHECK-ERRORS: str r1, [r2, r3, lsl #invalid]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: ldr r4, [r5], r6, lsl #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: pld r4, [r5, r6, lsl #32]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: str r4, [r5], r6, lsr #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: ldr r4, [r5, r6, lsr #33]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: pld r4, [r5, r6, asr #-1]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: str r4, [r5, r6, asr #33]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: ldr r4, [r5, r6, ror #-1]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: pld r4, [r5, r6, ror #32]
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@ CHECK-ERRORS: error: ']' expected
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@ CHECK-ERRORS: pld r4, [r5, r6, rrx #0]
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@ Out of range 16-bit immediate on BKPT
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bkpt #65536
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ Out of range immediates for v8 HLT instruction.
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hlt #65536
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hlt #-1
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@CHECK-ERRORS-V8: error: invalid operand for instruction
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@CHECK-ERRORS-V8: hlt #65536
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@CHECK-ERRORS-V8: ^
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@CHECK-ERRORS-V8: error: invalid operand for instruction
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@CHECK-ERRORS-V8: hlt #-1
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@CHECK-ERRORS-V8: ^
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@ Illegal condition code for v8 HLT instruction.
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hlteq #2
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hltlt #23
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@CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified
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@CHECK-ERRORS-V8: hlteq #2
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@CHECK-ERRORS-V8: ^
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@CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified
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@CHECK-ERRORS-V8: hltlt #23
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@CHECK-ERRORS-V8: ^
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@ Out of range 4 and 3 bit immediates on CDP[2]
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@ Out of range immediates for CDP/CDP2
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cdp p7, #2, c1, c1, c1, #8
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cdp p7, #1, c1, c1, c1, #8
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cdp2 p7, #2, c1, c1, c1, #8
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cdp2 p7, #1, c1, c1, c1, #8
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ Out of range immediates for DBG
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dbg #-1
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dbg #16
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ Double-check that we're synced up with the right diagnostics.
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@ CHECK-ERRORS: dbg #16
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@ Out of range immediate for MCR/MCR2/MCRR/MCRR2
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mcr p7, #8, r5, c1, c1, #4
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mcr p7, #2, r5, c1, c1, #8
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mcr2 p7, #8, r5, c1, c1, #4
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mcr2 p7, #1, r5, c1, c1, #8
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mcrr p7, #16, r5, r4, c1
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mcrr2 p7, #16, r5, r4, c1
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ p10 and p11 are reserved for NEON
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mcr p10, #2, r5, c1, c1, #4
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mcrr p11, #8, r5, r4, c1
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ Out of range immediate for MOV
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movw r9, 0x10000
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ Invalid 's' bit usage for MOVW
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movs r6, #0xffff
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movwseq r9, #0xffff
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: instruction 'movw' can not set flags, but 's' suffix specified
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@ Out of range immediate for MOVT
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movt r9, 0x10000
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ Out of range immediates for MRC/MRC2/MRRC/MRRC2
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mrc p14, #8, r1, c1, c2, #4
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mrc p14, #1, r1, c1, c2, #8
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mrc2 p14, #8, r1, c1, c2, #4
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mrc2 p14, #0, r1, c1, c2, #9
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mrrc p7, #16, r5, r4, c1
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mrrc2 p7, #17, r5, r4, c1
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ Shifter operand validation for PKH instructions.
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pkhbt r2, r2, r3, lsl #-1
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pkhbt r2, r2, r3, lsl #32
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pkhtb r2, r2, r3, asr #0
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pkhtb r2, r2, r3, asr #33
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pkhbt r2, r2, r3, asr #3
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pkhtb r2, r2, r3, lsl #3
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@ CHECK-ERRORS: error: immediate value out of range
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@ CHECK-ERRORS: pkhbt r2, r2, r3, lsl #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate value out of range
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@ CHECK-ERRORS: pkhbt r2, r2, r3, lsl #32
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate value out of range
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@ CHECK-ERRORS: pkhtb r2, r2, r3, asr #0
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate value out of range
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@ CHECK-ERRORS: pkhtb r2, r2, r3, asr #33
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: lsl operand expected.
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@ CHECK-ERRORS: pkhbt r2, r2, r3, asr #3
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: asr operand expected.
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@ CHECK-ERRORS: pkhtb r2, r2, r3, lsl #3
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@ CHECK-ERRORS: ^
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@ bad values for SETEND
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setendne be
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setend me
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setend 1
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@ CHECK-ERRORS: error: instruction 'setend' is not predicable, but condition code specified
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@ CHECK-ERRORS: setendne be
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'be' or 'le' operand expected
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@ CHECK-ERRORS: setend me
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'be' or 'le' operand expected
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@ CHECK-ERRORS: setend 1
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@ CHECK-ERRORS: ^
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@ Out of range immediates and bad shift types for SSAT
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ssat r8, #0, r10, lsl #8
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ssat r8, #33, r10, lsl #8
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ssat r8, #1, r10, lsl #-1
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ssat r8, #1, r10, lsl #32
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ssat r8, #1, r10, asr #0
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ssat r8, #1, r10, asr #33
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ssat r8, #1, r10, lsr #5
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ssat r8, #1, r10, lsl fred
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ssat r8, #1, r10, lsl #fred
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: ssat r8, #0, r10, lsl #8
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: ssat r8, #33, r10, lsl #8
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'lsr' shift amount must be in range [0,31]
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@ CHECK-ERRORS: ssat r8, #1, r10, lsl #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'lsr' shift amount must be in range [0,31]
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@ CHECK-ERRORS: ssat r8, #1, r10, lsl #32
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'asr' shift amount must be in range [1,32]
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@ CHECK-ERRORS: ssat r8, #1, r10, asr #0
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'asr' shift amount must be in range [1,32]
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@ CHECK-ERRORS: ssat r8, #1, r10, asr #33
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: shift operator 'asr' or 'lsl' expected
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@ CHECK-ERRORS: ssat r8, #1, r10, lsr #5
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: '#' expected
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@ CHECK-ERRORS: ssat r8, #1, r10, lsl fred
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: shift amount must be an immediate
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@ CHECK-ERRORS: ssat r8, #1, r10, lsl #fred
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@ CHECK-ERRORS: ^
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@ Out of range immediates for SSAT16
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ssat16 r2, #0, r7
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ssat16 r3, #17, r5
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: ssat16 r2, #0, r7
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: ssat16 r3, #17, r5
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@ CHECK-ERRORS: ^
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@ Out of order STM registers
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stmda sp!, {r5, r2}
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@ CHECK-ERRORS: warning: register list not in ascending order
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@ CHECK-ERRORS: stmda sp!, {r5, r2}
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@ CHECK-ERRORS: ^
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@ Out of range immediate on SVC
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svc #0x1000000
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: svc #0x1000000
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@ CHECK-ERRORS: ^
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@ Out of order Rt/Rt2 operands for ldrexd/strexd
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ldrexd r4, r3, [r8]
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strexd r6, r5, r3, [r8]
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@ CHECK-ERRORS: error: destination operands must be sequential
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@ CHECK-ERRORS: ldrexd r4, r3, [r8]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: source operands must be sequential
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@ CHECK-ERRORS: strexd r6, r5, r3, [r8]
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@ CHECK-ERRORS: ^
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@ Illegal rotate operators for extend instructions
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sxtb r8, r3, #8
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sxtb r8, r3, ror 24
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sxtb r8, r3, ror #8 -
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sxtab r3, r8, r3, ror #(fred - wilma)
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sxtab r7, r8, r3, ror #25
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sxtah r9, r3, r3, ror #-8
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sxtb16ge r2, r3, lsr #24
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: sxtb r8, r3, #8
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: '#' expected
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@ CHECK-ERRORS: sxtb r8, r3, ror 24
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: unknown token in expression
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@ CHECK-ERRORS: sxtb r8, r3, ror #8 -
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: malformed rotate expression
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@ CHECK-ERRORS: sxtb r8, r3, ror #8 -
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: rotate amount must be an immediate
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@ CHECK-ERRORS: sxtab r3, r8, r3, ror #(fred - wilma)
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24
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@ CHECK-ERRORS: sxtab r7, r8, r3, ror #25
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24
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@ CHECK-ERRORS: sxtah r9, r3, r3, ror #-8
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: sxtb16ge r2, r3, lsr #24
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@ CHECK-ERRORS: ^
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@ Out of range width for SBFX/UBFX
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sbfx r4, r5, #31, #2
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ubfxgt r4, r5, #16, #17
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@ CHECK-ERRORS: error: bitfield width must be in range [1,32-lsb]
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@ CHECK-ERRORS: sbfx r4, r5, #31, #2
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: bitfield width must be in range [1,32-lsb]
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@ CHECK-ERRORS: ubfxgt r4, r5, #16, #17
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@ CHECK-ERRORS: ^
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@ Using pc for SBFX/UBFX
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sbfx pc, r2, #1, #3
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sbfx sp, pc, #4, #5
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ubfx pc, r0, #0, #31
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ubfx r14, pc, #1, #2
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: sbfx pc, r2, #1, #3
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: sbfx sp, pc, #4, #5
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: ubfx pc, r0, #0, #31
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: ubfx r14, pc, #1, #2
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@ CHECK-ERRORS: ^
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@ Out of order Rt/Rt2 operands for ldrd
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ldrd r4, r3, [r8]
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ldrd r4, r3, [r8, #8]!
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ldrd r4, r3, [r8], #8
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@ CHECK-ERRORS: error: destination operands must be sequential
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@ CHECK-ERRORS: ldrd r4, r3, [r8]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: destination operands must be sequential
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@ CHECK-ERRORS: ldrd r4, r3, [r8, #8]!
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: destination operands must be sequential
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@ CHECK-ERRORS: ldrd r4, r3, [r8], #8
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@ CHECK-ERRORS: ^
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@ Bad register lists for VFP.
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vpush {s0, s3}
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@ CHECK-ERRORS: error: non-contiguous register range
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@ CHECK-ERRORS: vpush {s0, s3}
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@ CHECK-ERRORS: ^
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@ Out of range coprocessor option immediate.
|
|
ldc2 p2, c8, [r1], { 256 }
|
|
ldc2 p2, c8, [r1], { -1 }
|
|
|
|
@ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255]
|
|
@ CHECK-ERRORS: ldc2 p2, c8, [r1], { 256 }
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255]
|
|
@ CHECK-ERRORS: ldc2 p2, c8, [r1], { -1 }
|
|
@ CHECK-ERRORS: ^
|
|
|
|
@ Bad CPS instruction format.
|
|
cps f,#1
|
|
@ CHECK-ERRORS: error: invalid operand for instruction
|
|
@ CHECK-ERRORS: cps f,#1
|
|
@ CHECK-ERRORS: ^
|
|
|
|
@ Bad operands for msr
|
|
msr #0, #0
|
|
msr foo, #0
|
|
@ CHECK-ERRORS: error: invalid operand for instruction
|
|
@ CHECK-ERRORS: msr #0, #0
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: invalid operand for instruction
|
|
@ CHECK-ERRORS: msr foo, #0
|
|
@ CHECK-ERRORS: ^
|
|
|
|
isb #-1
|
|
isb #16
|
|
@ CHECK-ERRORS: error: immediate value out of range
|
|
@ CHECK-ERRORS: error: immediate value out of range
|
|
|
|
nop.n
|
|
@ CHECK-ERRORS: error: instruction with .n (narrow) qualifier not allowed in arm mode
|
|
|
|
dmbeq #5
|
|
dsble #15
|
|
isblo #7
|
|
@ CHECK-ERRORS: error: instruction 'dmb' is not predicable, but condition code specified
|
|
@ CHECK-ERRORS: error: instruction 'dsb' is not predicable, but condition code specified
|
|
@ CHECK-ERRORS: error: instruction 'isb' is not predicable, but condition code specified
|
|
|
|
dmblt
|
|
dsbne
|
|
isbeq
|
|
@ CHECK-ERRORS: error: instruction 'dmb' is not predicable, but condition code specified
|
|
@ CHECK-ERRORS: error: instruction 'dsb' is not predicable, but condition code specified
|
|
@ CHECK-ERRORS: error: instruction 'isb' is not predicable, but condition code specified
|
|
|
|
mcr2le p7, #1, r5, c1, c1, #4
|
|
mcrr2ne p7, #15, r5, r4, c1
|
|
mrc2lo p14, #0, r1, c1, c2, #4
|
|
mrrc2lo p7, #1, r5, r4, c1
|
|
cdp2hi p10, #0, c6, c12, c0, #7
|
|
@ CHECK-ERRORS: error: instruction 'mcr2' is not predicable, but condition code specified
|
|
@ CHECK-ERRORS: error: instruction 'mcrr2' is not predicable, but condition code specified
|
|
@ CHECK-ERRORS: error: instruction 'mrc2' is not predicable, but condition code specified
|
|
@ CHECK-ERRORS: error: instruction 'mrrc2' is not predicable, but condition code specified
|
|
@ CHECK-ERRORS: error: instruction 'cdp2' is not predicable, but condition code specified
|
|
|
|
bkpteq #7
|
|
@ CHECK-ERRORS: error: instruction 'bkpt' is not predicable, but condition code specified
|
|
|
|
ldm r2!, {r2, r3}
|
|
ldmdb r2!, {r2, r3}
|
|
ldmda r2!, {r2, r3}
|
|
popeq {sp}
|
|
@ CHECK-ERRORS: error: writeback register not allowed in register list
|
|
@ CHECK-ERRORS: error: writeback register not allowed in register list
|
|
@ CHECK-ERRORS: error: writeback register not allowed in register list
|
|
@ CHECK-ERRORS: error: writeback register not allowed in register list
|
|
|
|
vrintz.f32.f32 s0, s1
|
|
vrintr.f32 s0, s1
|
|
vrintx.f64.f64 d2, d5
|
|
vrintz.f64 d10, d9
|
|
vrinta.f32.f32 s6, s7
|
|
vrintn.f32 s8, s9
|
|
vrintp.f64.f64 d10, d11
|
|
vrintm.f64 d12, d13
|
|
@ CHECK-ERRORS: error: instruction requires: FPARMv8
|
|
@ CHECK-ERRORS: error: instruction requires: FPARMv8
|
|
@ CHECK-ERRORS: error: instruction requires: FPARMv8
|
|
@ CHECK-ERRORS: error: instruction requires: FPARMv8
|
|
@ CHECK-ERRORS: error: instruction requires: FPARMv8
|
|
@ CHECK-ERRORS: error: instruction requires: FPARMv8
|
|
@ CHECK-ERRORS: error: instruction requires: FPARMv8
|
|
@ CHECK-ERRORS: error: instruction requires: FPARMv8
|
|
|
|
stm sp!, {r0, pc}^
|
|
ldm sp!, {r0}^
|
|
@ CHECK-ERRORS: error: system STM cannot have writeback register
|
|
@ CHECK-ERRORS: error: writeback register only allowed on system LDM if PC in register-list
|
|
|
|
foo2:
|
|
mov r0, foo2
|
|
movw r0, foo2
|
|
@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16
|
|
@ CHECK-ERRORS: ^
|
|
|
|
str r0, [r0, #4]!
|
|
str r0, [r0, r1]!
|
|
str r0, [r0], #4
|
|
str r0, [r0], r1
|
|
strh r0, [r0, #2]!
|
|
strh r0, [r0, r1]!
|
|
strh r0, [r0], #2
|
|
strh r0, [r0], r1
|
|
strb r0, [r0, #1]!
|
|
strb r0, [r0, r1]!
|
|
strb r0, [r0], #1
|
|
strb r0, [r0], r1
|
|
@ CHECK-ERRORS: error: source register and base register can't be identical
|
|
@ CHECK-ERRORS: str r0, [r0, #4]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: source register and base register can't be identical
|
|
@ CHECK-ERRORS: str r0, [r0, r1]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: source register and base register can't be identical
|
|
@ CHECK-ERRORS: str r0, [r0], #4
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: source register and base register can't be identical
|
|
@ CHECK-ERRORS: str r0, [r0], r1
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: source register and base register can't be identical
|
|
@ CHECK-ERRORS: strh r0, [r0, #2]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: source register and base register can't be identical
|
|
@ CHECK-ERRORS: strh r0, [r0, r1]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: source register and base register can't be identical
|
|
@ CHECK-ERRORS: strh r0, [r0], #2
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: source register and base register can't be identical
|
|
@ CHECK-ERRORS: strh r0, [r0], r1
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: source register and base register can't be identical
|
|
@ CHECK-ERRORS: strb r0, [r0, #1]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: source register and base register can't be identical
|
|
@ CHECK-ERRORS: strb r0, [r0, r1]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: source register and base register can't be identical
|
|
@ CHECK-ERRORS: strb r0, [r0], #1
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: source register and base register can't be identical
|
|
@ CHECK-ERRORS: strb r0, [r0], r1
|
|
@ CHECK-ERRORS: ^
|
|
|
|
ldr r0, [r0, #4]!
|
|
ldr r0, [r0, r1]!
|
|
ldr r0, [r0], #4
|
|
ldr r0, [r0], r1
|
|
ldrh r0, [r0, #2]!
|
|
ldrh r0, [r0, r1]!
|
|
ldrh r0, [r0], #2
|
|
ldrh r0, [r0], r1
|
|
ldrsh r0, [r0, #2]!
|
|
ldrsh r0, [r0, r1]!
|
|
ldrsh r0, [r0], #2
|
|
ldrsh r0, [r0], r1
|
|
ldrb r0, [r0, #1]!
|
|
ldrb r0, [r0, r1]!
|
|
ldrb r0, [r0], #1
|
|
ldrb r0, [r0], r1
|
|
ldrsb r0, [r0, #1]!
|
|
ldrsb r0, [r0, r1]!
|
|
ldrsb r0, [r0], #1
|
|
ldrsb r0, [r0], r1
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldr r0, [r0, #4]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldr r0, [r0, r1]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldr r0, [r0], #4
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldr r0, [r0], r1
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrh r0, [r0, #2]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrh r0, [r0, r1]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrh r0, [r0], #2
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrh r0, [r0], r1
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrsh r0, [r0, #2]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrsh r0, [r0, r1]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrsh r0, [r0], #2
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrsh r0, [r0], r1
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrb r0, [r0, #1]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrb r0, [r0, r1]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrb r0, [r0], #1
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrb r0, [r0], r1
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrsb r0, [r0, #1]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrsb r0, [r0, r1]!
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrsb r0, [r0], #1
|
|
@ CHECK-ERRORS: ^
|
|
@ CHECK-ERRORS: error: destination register and base register can't be identical
|
|
@ CHECK-ERRORS: ldrsb r0, [r0], r1
|
|
@ CHECK-ERRORS: ^
|
|
|
|
@ Out of range modified immediate values
|
|
mov r5, #-256, #6
|
|
mov r6, #42, #7
|
|
mvn r5, #256, #6
|
|
mvn r6, #42, #298
|
|
cmp r5, #65535, #6
|
|
cmp r6, #42, #31
|
|
cmn r5, #-1, #6
|
|
cmn r6, #42, #32
|
|
msr APSR_nzcvq, #-128, #2
|
|
msr apsr_nzcvqg, #0, #1
|
|
adc r7, r8, #-256, #2
|
|
adc r7, r8, #128, #1
|
|
sbc r7, r8, #-256, #2
|
|
sbc r7, r8, #128, #1
|
|
add r7, r8, #-2149, #0
|
|
add r7, r8, #100, #1
|
|
sub r7, r8, #-2149, #0
|
|
sub r7, r8, #100, #1
|
|
and r7, r8, #-2149, #0
|
|
and r7, r8, #100, #1
|
|
orr r7, r8, #-2149, #0
|
|
orr r7, r8, #100, #1
|
|
eor r7, r8, #-2149, #0
|
|
eor r7, r8, #100, #1
|
|
bic r7, r8, #-2149, #0
|
|
bic r7, r8, #100, #1
|
|
rsb r7, r8, #-2149, #0
|
|
rsb r7, r8, #100, #1
|
|
adds r7, r8, #-2149, #0
|
|
adds r7, r8, #100, #1
|
|
subs r7, r8, #-2149, #0
|
|
subs r7, r8, #100, #1
|
|
rsbs r7, r8, #-2149, #0
|
|
rsbs r7, r8, #100, #1
|
|
rsc r7, r8, #-2149, #0
|
|
rsc r7, r8, #100, #1
|
|
TST r7, #-2149, #0
|
|
TST r7, #100, #1
|
|
TEQ r7, #-2149, #0
|
|
TEQ r7, #100, #1
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|
|
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
|
|
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
|