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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 22:04:55 +00:00
9c1911b105
The ARM Architecture Reference Manual states the following:
LDM{,IA,DB}:
The SP cannot be in the list.
The PC can be in the list.
If the PC is in the list:
• the LR must not be in the list
• the instruction must be either outside any IT block, or the last
instruction in an IT block.
POP:
The PC can be in the list.
If the PC is in the list:
• the LR must not be in the list
• the instruction must be either outside any IT block, or the last
instruction in an IT block.
PUSH:
The SP and PC can be in the list in ARM instructions, but not in Thumb
instructions.
STM:{,IA,DB}:
The SP and PC can be in the list in ARM instructions, but not in Thumb
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224502 91177308-0d34-0410-b5e6-96231b3b80d8
278 lines
10 KiB
ArmAsm
278 lines
10 KiB
ArmAsm
@ RUN: not llvm-mc -triple=thumbv6-apple-darwin -o /dev/null < %s 2>&1 \
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@ RUN: | FileCheck --check-prefix=CHECK-ERRORS %s
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@ RUN: not llvm-mc -triple=thumbv5-apple-darwin -o /dev/null < %s 2>&1 \
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@ RUN: | FileCheck --check-prefix=CHECK-ERRORS-V5 %s
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@ RUN: not llvm-mc -triple=thumbv7m -o /dev/null < %s 2>&1 \
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@ RUN: | FileCheck --check-prefix=CHECK-ERRORS-V7M %s
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@ RUN: not llvm-mc -triple=thumbv8 -o /dev/null < %s 2>&1 \
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@ RUN: | FileCheck --check-prefix=CHECK-ERRORS-V8 %s
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@ Check for various assembly diagnostic messages on invalid input.
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@ ADD instruction w/o 'S' suffix.
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add r1, r2, r3
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@ CHECK-ERRORS: error: invalid instruction
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@ CHECK-ERRORS: add r1, r2, r3
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@ CHECK-ERRORS: ^
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@ Instructions which require v6+ for both registers to be low regs.
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add r2, r3
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mov r2, r3
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@ CHECK-ERRORS: error: instruction variant requires Thumb2
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@ CHECK-ERRORS: add r2, r3
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS-V5: error: instruction variant requires ARMv6 or later
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@ CHECK-ERRORS-V5: mov r2, r3
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@ CHECK-ERRORS-V5: ^
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@ Out of range immediates for ASR instruction.
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asrs r2, r3, #33
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: asrs r2, r3, #33
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@ CHECK-ERRORS: ^
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@ Out of range immediates for BKPT instruction.
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bkpt #256
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bkpt #-1
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error: invalid operand for instruction
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bkpt #256
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^
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error: invalid operand for instruction
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bkpt #-1
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^
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@ Out of range immediates for v8 HLT instruction.
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hlt #64
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hlt #-1
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@CHECK-ERRORS: error: instruction requires: armv8 arm-mode
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@CHECK-ERRORS: hlt #64
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@CHECK-ERRORS: ^
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@CHECK-ERRORS-V8: error: instruction requires: arm-mode
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@CHECK-ERRORS-V8: hlt #64
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@CHECK-ERRORS-V8: ^
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@CHECK-ERRORS: error: invalid operand for instruction
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@CHECK-ERRORS: hlt #-1
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@CHECK-ERRORS: ^
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@ Invalid writeback and register lists for LDM
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ldm r2!, {r5, r8}
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ldm r2, {r5, r7}
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ldm r2!, {r2, r3, r4}
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ldm r2!, {r2, r3, r4, r10}
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ldmdb r2!, {r2, r3, r4}
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ldm r0, {r2, sp}
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ldmia r0, {r2-r3, sp}
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ldmia r0!, {r2-r3, sp}
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ldmfd r2, {r1, r3-r6, sp}
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ldmfd r2!, {r1, r3-r6, sp}
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ldmdb r1, {r2, r3, sp}
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ldmdb r1!, {r2, r3, sp}
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@ CHECK-ERRORS: error: registers must be in range r0-r7
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@ CHECK-ERRORS: ldm r2!, {r5, r8}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: writeback operator '!' expected
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@ CHECK-ERRORS: ldm r2, {r5, r7}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
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@ CHECK-ERRORS: ldm r2!, {r2, r3, r4}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
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@ CHECK-ERRORS-V8: ldm r2!, {r2, r3, r4, r10}
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@ CHECK-ERRORS-V8: ^
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@ CHECK-ERRORS-V8: error: writeback register not allowed in register list
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@ CHECK-ERRORS-V8: ldmdb r2!, {r2, r3, r4}
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@ CHECK-ERRORS-V8: ^
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@ CHECK-ERRORS-V7M: error: SP may not be in the register list
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@ CHECK-ERRORS-V7M: ldm r0, {r2, sp}
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@ CHECK-ERRORS-V7M: ^
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@ CHECK-ERRORS-V7M: error: SP may not be in the register list
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@ CHECK-ERRORS-V7M: ldmia r0, {r2-r3, sp}
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@ CHECK-ERRORS-V7M: ^
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@ CHECK-ERRORS-V7M: error: SP may not be in the register list
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@ CHECK-ERRORS-V7M: ldmia r0!, {r2-r3, sp}
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@ CHECK-ERRORS-V7M: ^
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@ CHECK-ERRORS-V7M: error: SP may not be in the register list
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@ CHECK-ERRORS-V7M: ldmfd r2, {r1, r3-r6, sp}
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@ CHECK-ERRORS-V7M: ^
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@ CHECK-ERRORS-V7M: error: SP may not be in the register list
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@ CHECK-ERRORS-V7M: ldmfd r2!, {r1, r3-r6, sp}
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@ CHECK-ERRORS-V7M: ^
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@ CHECK-ERRORS-V7M: error: SP may not be in the register list
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@ CHECK-ERRORS-V7M: ldmdb r1, {r2, r3, sp}
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@ CHECK-ERRORS-V7M: ^
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@ CHECK-ERRORS-V7M: error: SP may not be in the register list
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@ CHECK-ERRORS-V7M: ldmdb r1!, {r2, r3, sp}
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@ CHECK-ERRORS-V7M: ^
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@ Invalid writeback and register lists for PUSH/POP
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pop {r1, r2, r10}
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push {r8, r9}
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@ CHECK-ERRORS: error: registers must be in range r0-r7 or pc
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@ CHECK-ERRORS: pop {r1, r2, r10}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: registers must be in range r0-r7 or lr
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@ CHECK-ERRORS: push {r8, r9}
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@ CHECK-ERRORS: ^
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@ Invalid writeback and register lists for STM
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stm r1, {r2, r6}
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stm r1!, {r2, r9}
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stm r2!, {r2, r9}
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stmdb r2!, {r0, r2}
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stm r1!, {r2, sp}
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stmia r4!, {r0-r3, sp}
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stmdb r1, {r2, r3, sp}
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stmdb r1!, {r2, r3, sp}
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: stm r1, {r2, r6}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: registers must be in range r0-r7
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@ CHECK-ERRORS: stm r1!, {r2, r9}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
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@ CHECK-ERRORS-V8: stm r2!, {r2, r9}
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@ CHECK-ERRORS-V8: ^
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@ CHECK-ERRORS-V8: error: writeback register not allowed in register list
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@ CHECK-ERRORS-V8: stmdb r2!, {r0, r2}
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@ CHECK-ERRORS-V8: ^
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@ CHECK-ERRORS-V7M: error: SP may not be in the register list
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@ CHECK-ERRORS-V7M: stm r1!, {r2, sp}
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@ CHECK-ERRORS-V7M: ^
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@ CHECK-ERRORS-V7M: error: SP may not be in the register list
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@ CHECK-ERRORS-V7M: stmia r4!, {r0-r3, sp}
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@ CHECK-ERRORS-V7M: ^
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@ CHECK-ERRORS-V7M: error: SP may not be in the register list
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@ CHECK-ERRORS-V7M: stmdb r1, {r2, r3, sp}
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@ CHECK-ERRORS-V7M: ^
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@ CHECK-ERRORS-V7M: error: SP may not be in the register list
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@ CHECK-ERRORS-V7M: stmdb r1!, {r2, r3, sp}
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@ CHECK-ERRORS-V7M: ^
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@ Out of range immediates for LSL instruction.
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lsls r4, r5, #-1
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lsls r4, r5, #32
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: lsls r4, r5, #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: lsls r4, r5, #32
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@ CHECK-ERRORS: ^
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@ Mismatched source/destination operands for MUL instruction.
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muls r1, r2, r3
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@ CHECK-ERRORS: error: destination register must match source register
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@ CHECK-ERRORS: muls r1, r2, r3
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@ CHECK-ERRORS: ^
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@ Out of range immediates for STR instruction.
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str r2, [r7, #-1]
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str r5, [r1, #3]
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str r3, [r7, #128]
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: str r2, [r7, #-1]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: str r5, [r1, #3]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: str r3, [r7, #128]
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@ CHECK-ERRORS: ^
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@ Out of range immediate for SVC instruction.
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svc #-1
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svc #256
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: svc #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: arm-mode
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@ CHECK-ERRORS: svc #256
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@ CHECK-ERRORS: ^
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@ Out of range immediate for ADD SP instructions
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add sp, #-1
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add sp, #3
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add sp, sp, #512
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add r2, sp, #1024
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: add sp, #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: add sp, #3
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: add sp, sp, #512
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: add r2, sp, #1024
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@ CHECK-ERRORS: ^
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add r2, sp, ip
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@ CHECK-ERRORS: error: source register must be the same as destination
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@ CHECK-ERRORS: add r2, sp, ip
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@ CHECK-ERRORS: ^
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@------------------------------------------------------------------------------
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@ B/Bcc - out of range immediates for Thumb1 branches
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@------------------------------------------------------------------------------
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beq #-258
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bne #256
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bgt #13
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b #-1048578
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b #1048576
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b #10323
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@ CHECK-ERRORS: error: branch target out of range
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@ CHECK-ERRORS: error: branch target out of range
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@ CHECK-ERRORS: error: branch target out of range
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@ CHECK-ERRORS: error: branch target out of range
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@ CHECK-ERRORS: error: branch target out of range
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@ CHECK-ERRORS: error: branch target out of range
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@------------------------------------------------------------------------------
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@ WFE/WFI/YIELD - are not supported pre v6T2
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@------------------------------------------------------------------------------
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wfe
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wfi
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yield
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@ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
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@ CHECK-ERRORS: wfe
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
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@ CHECK-ERRORS: wfi
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
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@ CHECK-ERRORS: yield
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@ CHECK-ERRORS: ^
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@------------------------------------------------------------------------------
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@ PLDW required mp-extensions
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@------------------------------------------------------------------------------
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pldw [r0, #4]
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@ CHECK-ERRORS: error: instruction requires: mp-extensions
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@------------------------------------------------------------------------------
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@ LDR(lit) - invalid offsets
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@------------------------------------------------------------------------------
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ldr r4, [pc, #-12]
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@------------------------------------------------------------------------------
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@ STC2{L}/LDC2{L} - requires thumb2
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@------------------------------------------------------------------------------
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stc2 p0, c8, [r1, #4]
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stc2l p6, c2, [r7, #4]
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ldc2 p0, c8, [r1, #4]
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ldc2l p6, c2, [r7, #4]
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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