mirror of
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into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
495 lines
20 KiB
C++
495 lines
20 KiB
C++
//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass eliminates machine instruction PHI nodes by inserting copy
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// instructions. This destroys SSA information, but is the desired input for
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// some register allocators.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "phielim"
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#include "llvm/CodeGen/Passes.h"
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#include "PHIEliminationUtils.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include <algorithm>
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using namespace llvm;
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static cl::opt<bool>
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DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
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cl::Hidden, cl::desc("Disable critical edge splitting "
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"during PHI elimination"));
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namespace {
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class PHIElimination : public MachineFunctionPass {
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MachineRegisterInfo *MRI; // Machine register information
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public:
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static char ID; // Pass identification, replacement for typeid
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PHIElimination() : MachineFunctionPass(ID) {
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initializePHIEliminationPass(*PassRegistry::getPassRegistry());
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}
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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private:
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/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
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/// in predecessor basic blocks.
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///
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bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
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void LowerAtomicPHINode(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator AfterPHIsIt);
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/// analyzePHINodes - Gather information about the PHI nodes in
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/// here. In particular, we want to map the number of uses of a virtual
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/// register which is used in a PHI node. We map that to the BB the
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/// vreg is coming from. This is used later to determine when the vreg
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/// is killed in the BB.
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///
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void analyzePHINodes(const MachineFunction& Fn);
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/// Split critical edges where necessary for good coalescer performance.
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bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
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LiveVariables &LV, MachineLoopInfo *MLI);
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typedef std::pair<unsigned, unsigned> BBVRegPair;
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typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
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VRegPHIUse VRegPHIUseCount;
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// Defs of PHI sources which are implicit_def.
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SmallPtrSet<MachineInstr*, 4> ImpDefs;
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// Map reusable lowered PHI node -> incoming join register.
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typedef DenseMap<MachineInstr*, unsigned,
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MachineInstrExpressionTrait> LoweredPHIMap;
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LoweredPHIMap LoweredPHIs;
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};
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}
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STATISTIC(NumAtomic, "Number of atomic phis lowered");
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STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
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STATISTIC(NumReused, "Number of reused lowered phis");
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char PHIElimination::ID = 0;
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char& llvm::PHIEliminationID = PHIElimination::ID;
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INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination",
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"Eliminate PHI nodes for register allocation",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveVariables)
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INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination",
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"Eliminate PHI nodes for register allocation", false, false)
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void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addPreserved<LiveVariables>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addPreserved<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
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MRI = &MF.getRegInfo();
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bool Changed = false;
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// This pass takes the function out of SSA form.
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MRI->leaveSSA();
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// Split critical edges to help the coalescer
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if (!DisableEdgeSplitting) {
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if (LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>()) {
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MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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Changed |= SplitPHIEdges(MF, *I, *LV, MLI);
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}
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}
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// Populate VRegPHIUseCount
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analyzePHINodes(MF);
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// Eliminate PHI instructions by inserting copies into predecessor blocks.
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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Changed |= EliminatePHINodes(MF, *I);
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// Remove dead IMPLICIT_DEF instructions.
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for (SmallPtrSet<MachineInstr*, 4>::iterator I = ImpDefs.begin(),
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E = ImpDefs.end(); I != E; ++I) {
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MachineInstr *DefMI = *I;
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unsigned DefReg = DefMI->getOperand(0).getReg();
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if (MRI->use_nodbg_empty(DefReg))
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DefMI->eraseFromParent();
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}
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// Clean up the lowered PHI instructions.
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for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
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I != E; ++I)
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MF.DeleteMachineInstr(I->first);
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LoweredPHIs.clear();
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ImpDefs.clear();
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VRegPHIUseCount.clear();
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return Changed;
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}
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/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
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/// predecessor basic blocks.
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///
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bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
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MachineBasicBlock &MBB) {
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if (MBB.empty() || !MBB.front().isPHI())
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return false; // Quick exit for basic blocks without PHIs.
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// Get an iterator to the first instruction after the last PHI node (this may
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// also be the end of the basic block).
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MachineBasicBlock::iterator AfterPHIsIt = MBB.SkipPHIsAndLabels(MBB.begin());
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while (MBB.front().isPHI())
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LowerAtomicPHINode(MBB, AfterPHIsIt);
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return true;
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}
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/// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
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/// This includes registers with no defs.
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static bool isImplicitlyDefined(unsigned VirtReg,
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const MachineRegisterInfo *MRI) {
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for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(VirtReg),
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DE = MRI->def_end(); DI != DE; ++DI)
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if (!DI->isImplicitDef())
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return false;
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return true;
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}
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/// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
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/// are implicit_def's.
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static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
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const MachineRegisterInfo *MRI) {
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for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
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if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
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return false;
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return true;
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}
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/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
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/// under the assumption that it needs to be lowered in a way that supports
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/// atomic execution of PHIs. This lowering method is always correct all of the
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/// time.
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///
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void PHIElimination::LowerAtomicPHINode(
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator AfterPHIsIt) {
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++NumAtomic;
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// Unlink the PHI node from the basic block, but don't delete the PHI yet.
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MachineInstr *MPhi = MBB.remove(MBB.begin());
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unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
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unsigned DestReg = MPhi->getOperand(0).getReg();
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assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
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bool isDead = MPhi->getOperand(0).isDead();
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// Create a new register for the incoming PHI arguments.
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MachineFunction &MF = *MBB.getParent();
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unsigned IncomingReg = 0;
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bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
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// Insert a register to register copy at the top of the current block (but
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// after any remaining phi nodes) which copies the new incoming register
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// into the phi node destination.
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const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
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if (isSourceDefinedByImplicitDef(MPhi, MRI))
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// If all sources of a PHI node are implicit_def, just emit an
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// implicit_def instead of a copy.
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BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
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TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
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else {
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// Can we reuse an earlier PHI node? This only happens for critical edges,
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// typically those created by tail duplication.
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unsigned &entry = LoweredPHIs[MPhi];
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if (entry) {
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// An identical PHI node was already lowered. Reuse the incoming register.
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IncomingReg = entry;
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reusedIncoming = true;
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++NumReused;
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DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
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} else {
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const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
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entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
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}
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BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
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TII->get(TargetOpcode::COPY), DestReg)
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.addReg(IncomingReg);
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}
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// Update live variable information if there is any.
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LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>();
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if (LV) {
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MachineInstr *PHICopy = prior(AfterPHIsIt);
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if (IncomingReg) {
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LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
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// Increment use count of the newly created virtual register.
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LV->setPHIJoin(IncomingReg);
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// When we are reusing the incoming register, it may already have been
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// killed in this block. The old kill will also have been inserted at
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// AfterPHIsIt, so it appears before the current PHICopy.
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if (reusedIncoming)
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if (MachineInstr *OldKill = VI.findKill(&MBB)) {
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DEBUG(dbgs() << "Remove old kill from " << *OldKill);
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LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
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DEBUG(MBB.dump());
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}
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// Add information to LiveVariables to know that the incoming value is
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// killed. Note that because the value is defined in several places (once
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// each for each incoming block), the "def" block and instruction fields
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// for the VarInfo is not filled in.
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LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
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}
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// Since we are going to be deleting the PHI node, if it is the last use of
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// any registers, or if the value itself is dead, we need to move this
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// information over to the new copy we just inserted.
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LV->removeVirtualRegistersKilled(MPhi);
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// If the result is dead, update LV.
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if (isDead) {
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LV->addVirtualRegisterDead(DestReg, PHICopy);
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LV->removeVirtualRegisterDead(DestReg, MPhi);
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}
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}
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// Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
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for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
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--VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
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MPhi->getOperand(i).getReg())];
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// Now loop over all of the incoming arguments, changing them to copy into the
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// IncomingReg register in the corresponding predecessor basic block.
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SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
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for (int i = NumSrcs - 1; i >= 0; --i) {
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unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
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unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
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bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
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isImplicitlyDefined(SrcReg, MRI);
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assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
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"Machine PHI Operands must all be virtual registers!");
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// Get the MachineBasicBlock equivalent of the BasicBlock that is the source
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// path the PHI.
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MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
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// Check to make sure we haven't already emitted the copy for this block.
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// This can happen because PHI nodes may have multiple entries for the same
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// basic block.
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if (!MBBsInsertedInto.insert(&opBlock))
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continue; // If the copy has already been emitted, we're done.
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// Find a safe location to insert the copy, this may be the first terminator
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// in the block (or end()).
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MachineBasicBlock::iterator InsertPos =
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findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
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// Insert the copy.
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if (!reusedIncoming && IncomingReg) {
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if (SrcUndef) {
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// The source register is undefined, so there is no need for a real
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// COPY, but we still need to ensure joint dominance by defs.
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// Insert an IMPLICIT_DEF instruction.
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BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
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TII->get(TargetOpcode::IMPLICIT_DEF), IncomingReg);
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// Clean up the old implicit-def, if there even was one.
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if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
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if (DefMI->isImplicitDef())
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ImpDefs.insert(DefMI);
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} else {
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BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
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TII->get(TargetOpcode::COPY), IncomingReg)
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.addReg(SrcReg, 0, SrcSubReg);
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}
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}
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// Now update live variable information if we have it. Otherwise we're done
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if (SrcUndef || !LV) continue;
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// We want to be able to insert a kill of the register if this PHI (aka, the
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// copy we just inserted) is the last use of the source value. Live
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// variable analysis conservatively handles this by saying that the value is
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// live until the end of the block the PHI entry lives in. If the value
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// really is dead at the PHI copy, there will be no successor blocks which
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// have the value live-in.
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// Also check to see if this register is in use by another PHI node which
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// has not yet been eliminated. If so, it will be killed at an appropriate
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// point later.
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// Is it used by any PHI instructions in this block?
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bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)];
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// Okay, if we now know that the value is not live out of the block, we can
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// add a kill marker in this block saying that it kills the incoming value!
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if (!ValueIsUsed && !LV->isLiveOut(SrcReg, opBlock)) {
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// In our final twist, we have to decide which instruction kills the
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// register. In most cases this is the copy, however, terminator
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// instructions at the end of the block may also use the value. In this
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// case, we should mark the last such terminator as being the killing
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// block, not the copy.
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MachineBasicBlock::iterator KillInst = opBlock.end();
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MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
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for (MachineBasicBlock::iterator Term = FirstTerm;
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Term != opBlock.end(); ++Term) {
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if (Term->readsRegister(SrcReg))
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KillInst = Term;
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}
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if (KillInst == opBlock.end()) {
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// No terminator uses the register.
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if (reusedIncoming || !IncomingReg) {
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// We may have to rewind a bit if we didn't insert a copy this time.
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KillInst = FirstTerm;
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while (KillInst != opBlock.begin()) {
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--KillInst;
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if (KillInst->isDebugValue())
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continue;
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if (KillInst->readsRegister(SrcReg))
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break;
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}
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} else {
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// We just inserted this copy.
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KillInst = prior(InsertPos);
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}
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}
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assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
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// Finally, mark it killed.
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LV->addVirtualRegisterKilled(SrcReg, KillInst);
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// This vreg no longer lives all of the way through opBlock.
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unsigned opBlockNum = opBlock.getNumber();
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LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
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}
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}
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// Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
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if (reusedIncoming || !IncomingReg)
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MF.DeleteMachineInstr(MPhi);
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}
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/// analyzePHINodes - Gather information about the PHI nodes in here. In
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/// particular, we want to map the number of uses of a virtual register which is
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/// used in a PHI node. We map that to the BB the vreg is coming from. This is
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/// used later to determine when the vreg is killed in the BB.
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///
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void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
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for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
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I != E; ++I)
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for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
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BBI != BBE && BBI->isPHI(); ++BBI)
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for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
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++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i+1).getMBB()->getNumber(),
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BBI->getOperand(i).getReg())];
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}
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bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
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MachineBasicBlock &MBB,
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LiveVariables &LV,
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MachineLoopInfo *MLI) {
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if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad())
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return false; // Quick exit for basic blocks without PHIs.
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const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : 0;
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bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
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bool Changed = false;
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for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
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BBI != BBE && BBI->isPHI(); ++BBI) {
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for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
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unsigned Reg = BBI->getOperand(i).getReg();
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MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
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// Is there a critical edge from PreMBB to MBB?
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if (PreMBB->succ_size() == 1)
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continue;
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// Avoid splitting backedges of loops. It would introduce small
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// out-of-line blocks into the loop which is very bad for code placement.
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if (PreMBB == &MBB)
|
|
continue;
|
|
const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : 0;
|
|
if (IsLoopHeader && PreLoop == CurLoop)
|
|
continue;
|
|
|
|
// LV doesn't consider a phi use live-out, so isLiveOut only returns true
|
|
// when the source register is live-out for some other reason than a phi
|
|
// use. That means the copy we will insert in PreMBB won't be a kill, and
|
|
// there is a risk it may not be coalesced away.
|
|
//
|
|
// If the copy would be a kill, there is no need to split the edge.
|
|
if (!LV.isLiveOut(Reg, *PreMBB))
|
|
continue;
|
|
|
|
DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
|
|
<< PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
|
|
<< ": " << *BBI);
|
|
|
|
// If Reg is not live-in to MBB, it means it must be live-in to some
|
|
// other PreMBB successor, and we can avoid the interference by splitting
|
|
// the edge.
|
|
//
|
|
// If Reg *is* live-in to MBB, the interference is inevitable and a copy
|
|
// is likely to be left after coalescing. If we are looking at a loop
|
|
// exiting edge, split it so we won't insert code in the loop, otherwise
|
|
// don't bother.
|
|
bool ShouldSplit = !LV.isLiveIn(Reg, MBB);
|
|
|
|
// Check for a loop exiting edge.
|
|
if (!ShouldSplit && CurLoop != PreLoop) {
|
|
DEBUG({
|
|
dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
|
|
if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
|
|
if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
|
|
});
|
|
// This edge could be entering a loop, exiting a loop, or it could be
|
|
// both: Jumping directly form one loop to the header of a sibling
|
|
// loop.
|
|
// Split unless this edge is entering CurLoop from an outer loop.
|
|
ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
|
|
}
|
|
if (!ShouldSplit)
|
|
continue;
|
|
if (!PreMBB->SplitCriticalEdge(&MBB, this)) {
|
|
DEBUG(dbgs() << "Failed to split ciritcal edge.\n");
|
|
continue;
|
|
}
|
|
Changed = true;
|
|
++NumCriticalEdgesSplit;
|
|
}
|
|
}
|
|
return Changed;
|
|
}
|