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https://github.com/c64scene-ar/llvm-6502.git
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5e9ae090d8
The constraints are represented by the register class of the original virtual register created for the inline asm. If the register class were included in the operand descriptor, we might be able to do this. For now, just give up on regclass inflation when inline asm is involved. No test case, this bug hasn't happened yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134226 91177308-0d34-0410-b5e6-96231b3b80d8
220 lines
7.2 KiB
C++
220 lines
7.2 KiB
C++
//===------------------------ CalcSpillWeights.cpp ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "calcspillweights"
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#include "llvm/Function.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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char CalculateSpillWeights::ID = 0;
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INITIALIZE_PASS_BEGIN(CalculateSpillWeights, "calcspillweights",
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"Calculate spill weights", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
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INITIALIZE_PASS_END(CalculateSpillWeights, "calcspillweights",
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"Calculate spill weights", false, false)
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void CalculateSpillWeights::getAnalysisUsage(AnalysisUsage &au) const {
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au.addRequired<LiveIntervals>();
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au.addRequired<MachineLoopInfo>();
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au.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(au);
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}
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bool CalculateSpillWeights::runOnMachineFunction(MachineFunction &fn) {
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DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
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<< "********** Function: "
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<< fn.getFunction()->getName() << '\n');
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LiveIntervals &lis = getAnalysis<LiveIntervals>();
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VirtRegAuxInfo vrai(fn, lis, getAnalysis<MachineLoopInfo>());
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for (LiveIntervals::iterator I = lis.begin(), E = lis.end(); I != E; ++I) {
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LiveInterval &li = *I->second;
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if (TargetRegisterInfo::isVirtualRegister(li.reg))
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vrai.CalculateWeightAndHint(li);
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}
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return false;
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}
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// Return the preferred allocation register for reg, given a COPY instruction.
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static unsigned copyHint(const MachineInstr *mi, unsigned reg,
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const TargetRegisterInfo &tri,
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const MachineRegisterInfo &mri) {
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unsigned sub, hreg, hsub;
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if (mi->getOperand(0).getReg() == reg) {
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sub = mi->getOperand(0).getSubReg();
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hreg = mi->getOperand(1).getReg();
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hsub = mi->getOperand(1).getSubReg();
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} else {
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sub = mi->getOperand(1).getSubReg();
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hreg = mi->getOperand(0).getReg();
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hsub = mi->getOperand(0).getSubReg();
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}
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if (!hreg)
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return 0;
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if (TargetRegisterInfo::isVirtualRegister(hreg))
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return sub == hsub ? hreg : 0;
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const TargetRegisterClass *rc = mri.getRegClass(reg);
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// Only allow physreg hints in rc.
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if (sub == 0)
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return rc->contains(hreg) ? hreg : 0;
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// reg:sub should match the physreg hreg.
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return tri.getMatchingSuperReg(hreg, sub, rc);
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}
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void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
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MachineRegisterInfo &mri = MF.getRegInfo();
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const TargetRegisterInfo &tri = *MF.getTarget().getRegisterInfo();
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MachineBasicBlock *mbb = 0;
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MachineLoop *loop = 0;
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unsigned loopDepth = 0;
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bool isExiting = false;
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float totalWeight = 0;
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SmallPtrSet<MachineInstr*, 8> visited;
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// Find the best physreg hist and the best virtreg hint.
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float bestPhys = 0, bestVirt = 0;
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unsigned hintPhys = 0, hintVirt = 0;
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// Don't recompute a target specific hint.
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bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
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// Don't recompute spill weight for an unspillable register.
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bool Spillable = li.isSpillable();
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for (MachineRegisterInfo::reg_iterator I = mri.reg_begin(li.reg);
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MachineInstr *mi = I.skipInstruction();) {
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if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugValue())
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continue;
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if (!visited.insert(mi))
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continue;
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float weight = 1.0f;
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if (Spillable) {
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// Get loop info for mi.
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if (mi->getParent() != mbb) {
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mbb = mi->getParent();
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loop = Loops.getLoopFor(mbb);
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loopDepth = loop ? loop->getLoopDepth() : 0;
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isExiting = loop ? loop->isLoopExiting(mbb) : false;
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}
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// Calculate instr weight.
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bool reads, writes;
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tie(reads, writes) = mi->readsWritesVirtualRegister(li.reg);
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weight = LiveIntervals::getSpillWeight(writes, reads, loopDepth);
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// Give extra weight to what looks like a loop induction variable update.
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if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
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weight *= 3;
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totalWeight += weight;
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}
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// Get allocation hints from copies.
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if (noHint || !mi->isCopy())
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continue;
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unsigned hint = copyHint(mi, li.reg, tri, mri);
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if (!hint)
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continue;
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float hweight = Hint[hint] += weight;
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if (TargetRegisterInfo::isPhysicalRegister(hint)) {
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if (hweight > bestPhys && LIS.isAllocatable(hint))
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bestPhys = hweight, hintPhys = hint;
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} else {
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if (hweight > bestVirt)
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bestVirt = hweight, hintVirt = hint;
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}
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}
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Hint.clear();
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// Always prefer the physreg hint.
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if (unsigned hint = hintPhys ? hintPhys : hintVirt) {
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mri.setRegAllocationHint(li.reg, 0, hint);
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// Weakly boost the spill weight of hinted registers.
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totalWeight *= 1.01F;
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}
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// If the live interval was already unspillable, leave it that way.
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if (!Spillable)
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return;
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// Mark li as unspillable if all live ranges are tiny.
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if (li.isZeroLength(LIS.getSlotIndexes())) {
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li.markNotSpillable();
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return;
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}
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// If all of the definitions of the interval are re-materializable,
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// it is a preferred candidate for spilling. If none of the defs are
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// loads, then it's potentially very cheap to re-materialize.
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// FIXME: this gets much more complicated once we support non-trivial
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// re-materialization.
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bool isLoad = false;
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if (LIS.isReMaterializable(li, 0, isLoad)) {
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if (isLoad)
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totalWeight *= 0.9F;
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else
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totalWeight *= 0.5F;
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}
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li.weight = normalizeSpillWeight(totalWeight, li.getSize());
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}
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void VirtRegAuxInfo::CalculateRegClass(unsigned reg) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
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const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
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const TargetRegisterClass *OldRC = MRI.getRegClass(reg);
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const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
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// Stop early if there is no room to grow.
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if (NewRC == OldRC)
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return;
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// Accumulate constraints from all uses.
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for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(reg),
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E = MRI.reg_nodbg_end(); I != E; ++I) {
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// TRI doesn't have accurate enough information to model this yet.
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if (I.getOperand().getSubReg())
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return;
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// Inline asm instuctions don't remember their constraints.
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if (I->isInlineAsm())
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return;
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const TargetRegisterClass *OpRC =
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TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI);
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if (OpRC)
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NewRC = getCommonSubClass(NewRC, OpRC);
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if (!NewRC || NewRC == OldRC)
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return;
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}
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DEBUG(dbgs() << "Inflating " << OldRC->getName() << ':' << PrintReg(reg)
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<< " to " << NewRC->getName() <<".\n");
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MRI.setRegClass(reg, NewRC);
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}
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