mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8879480ed7
The LiveRegMatrix represents the live range of assigned virtual registers in a Live interval union per register unit. This is not fundamentally different from the interference tracking in RegAllocBase that both RABasic and RAGreedy use. The important differences are: - LiveRegMatrix tracks interference per register unit instead of per physical register. This makes interference checks cheaper and assignments slightly more expensive. For example, the ARM D7 reigster has 24 aliases, so we would check 24 physregs before assigning to one. With unit-based interference, we check 2 units before assigning to 2 units. - LiveRegMatrix caches regmask interference checks. That is currently duplicated functionality in RABasic and RAGreedy. - LiveRegMatrix is a pass which makes it possible to insert target-dependent passes between register allocation and rewriting. Such passes could tweak the register assignments with interference checking support from LiveRegMatrix. Eventually, RABasic and RAGreedy will be switched to LiveRegMatrix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158255 91177308-0d34-0410-b5e6-96231b3b80d8
110 lines
2.4 KiB
CMake
110 lines
2.4 KiB
CMake
add_llvm_library(LLVMCodeGen
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AggressiveAntiDepBreaker.cpp
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AllocationOrder.cpp
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Analysis.cpp
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BranchFolding.cpp
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CalcSpillWeights.cpp
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CallingConvLower.cpp
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CodeGen.cpp
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CodePlacementOpt.cpp
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CriticalAntiDepBreaker.cpp
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DeadMachineInstructionElim.cpp
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DFAPacketizer.cpp
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DwarfEHPrepare.cpp
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EdgeBundles.cpp
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ExecutionDepsFix.cpp
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ExpandISelPseudos.cpp
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ExpandPostRAPseudos.cpp
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GCMetadata.cpp
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GCMetadataPrinter.cpp
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GCStrategy.cpp
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IfConversion.cpp
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InlineSpiller.cpp
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InterferenceCache.cpp
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IntrinsicLowering.cpp
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JITCodeEmitter.cpp
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LLVMTargetMachine.cpp
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LatencyPriorityQueue.cpp
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LexicalScopes.cpp
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LiveDebugVariables.cpp
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LiveInterval.cpp
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LiveIntervalAnalysis.cpp
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LiveIntervalUnion.cpp
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LiveRegMatrix.cpp
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LiveStackAnalysis.cpp
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LiveVariables.cpp
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LiveRangeCalc.cpp
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LiveRangeEdit.cpp
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LocalStackSlotAllocation.cpp
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MachineBasicBlock.cpp
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MachineBlockFrequencyInfo.cpp
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MachineBlockPlacement.cpp
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MachineBranchProbabilityInfo.cpp
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MachineCodeEmitter.cpp
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MachineCopyPropagation.cpp
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MachineCSE.cpp
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MachineDominators.cpp
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MachineFunction.cpp
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MachineFunctionAnalysis.cpp
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MachineFunctionPass.cpp
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MachineFunctionPrinterPass.cpp
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MachineInstr.cpp
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MachineInstrBundle.cpp
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MachineLICM.cpp
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MachineLoopInfo.cpp
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MachineLoopRanges.cpp
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MachineModuleInfo.cpp
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MachineModuleInfoImpls.cpp
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MachinePassRegistry.cpp
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MachineRegisterInfo.cpp
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MachineSSAUpdater.cpp
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MachineScheduler.cpp
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MachineSink.cpp
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MachineVerifier.cpp
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OcamlGC.cpp
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OptimizePHIs.cpp
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PHIElimination.cpp
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PHIEliminationUtils.cpp
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Passes.cpp
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PeepholeOptimizer.cpp
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PostRASchedulerList.cpp
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ProcessImplicitDefs.cpp
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PrologEpilogInserter.cpp
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PseudoSourceValue.cpp
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RegAllocBase.cpp
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RegAllocBasic.cpp
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RegAllocFast.cpp
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RegAllocGreedy.cpp
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RegAllocPBQP.cpp
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RegisterClassInfo.cpp
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RegisterCoalescer.cpp
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RegisterPressure.cpp
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RegisterScavenging.cpp
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RenderMachineFunction.cpp
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ScheduleDAG.cpp
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ScheduleDAGInstrs.cpp
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ScheduleDAGPrinter.cpp
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ScoreboardHazardRecognizer.cpp
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ShadowStackGC.cpp
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ShrinkWrapping.cpp
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SjLjEHPrepare.cpp
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SlotIndexes.cpp
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Spiller.cpp
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SpillPlacement.cpp
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SplitKit.cpp
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StackProtector.cpp
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StackSlotColoring.cpp
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StrongPHIElimination.cpp
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TailDuplication.cpp
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TargetFrameLoweringImpl.cpp
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TargetInstrInfoImpl.cpp
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TargetLoweringObjectFileImpl.cpp
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TargetOptionsImpl.cpp
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TwoAddressInstructionPass.cpp
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UnreachableBlockElim.cpp
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VirtRegMap.cpp
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)
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add_subdirectory(SelectionDAG)
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add_subdirectory(AsmPrinter)
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