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instruction. This can happen on ARM: >> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0 Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031* Killing last use: %reg1028 Allocating %reg1035 from QPR Assigning %reg1035 to Q1 << %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104056 91177308-0d34-0410-b5e6-96231b3b80d8
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