mirror of
https://github.com/c64scene-ar/llvm-6502.git
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44de83a7f6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150902 91177308-0d34-0410-b5e6-96231b3b80d8
308 lines
14 KiB
TableGen
308 lines
14 KiB
TableGen
//===-- X86InstrXOP.td - XOP Instruction Set ---------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes XOP (eXtended OPerations)
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//
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//===----------------------------------------------------------------------===//
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multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int VR128:$src))]>, VEX;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, VEX;
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}
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let isAsmParserOnly = 1 in {
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defm VPHSUBWD : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, memopv2i64>;
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defm VPHSUBDQ : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, memopv2i64>;
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defm VPHSUBBW : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, memopv2i64>;
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defm VPHADDWQ : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, memopv2i64>;
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defm VPHADDWD : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, memopv2i64>;
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defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, memopv2i64>;
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defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, memopv2i64>;
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defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, memopv2i64>;
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defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, memopv2i64>;
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defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, memopv2i64>;
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defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, memopv2i64>;
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defm VPHADDDQ : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, memopv2i64>;
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defm VPHADDBW : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, memopv2i64>;
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defm VPHADDBQ : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, memopv2i64>;
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defm VPHADDBD : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, memopv2i64>;
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defm VFRCZPS : xop2op<0x80, "vfrczps", int_x86_xop_vfrcz_ps, memopv4f32>;
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defm VFRCZPD : xop2op<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, memopv2f64>;
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}
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// Scalar load 2 addr operand instructions
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let Constraints = "$src1 = $dst" in {
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multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
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Operand memop, ComplexPattern mem_cpat> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1,
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VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, VEX;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1,
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memop:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (Int VR128:$src1,
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(bitconvert mem_cpat:$src2)))]>, VEX;
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}
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} // Constraints = "$src1 = $dst"
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let isAsmParserOnly = 1 in {
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defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss,
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ssmem, sse_load_f32>;
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defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd,
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sdmem, sse_load_f64>;
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}
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multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
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PatFrag memop> {
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def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (Int VR256:$src))]>, VEX, VEX_L;
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def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, VEX;
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}
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let isAsmParserOnly = 1 in {
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defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256,
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memopv8f32>;
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defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256,
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memopv4f64>;
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}
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multiclass xop3op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, VEX_4VOp3;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))]>,
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VEX_4V, VEX_W;
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def mr : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
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(ins f128mem:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(Int (bitconvert (memopv2i64 addr:$src1)), VR128:$src2))]>,
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VEX_4VOp3;
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}
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let isAsmParserOnly = 1 in {
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defm VPSHLW : xop3op<0x95, "vpshlw", int_x86_xop_vpshlw>;
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defm VPSHLQ : xop3op<0x97, "vpshlq", int_x86_xop_vpshlq>;
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defm VPSHLD : xop3op<0x96, "vpshld", int_x86_xop_vpshld>;
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defm VPSHLB : xop3op<0x94, "vpshlb", int_x86_xop_vpshlb>;
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defm VPSHAW : xop3op<0x99, "vpshaw", int_x86_xop_vpshaw>;
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defm VPSHAQ : xop3op<0x9B, "vpshaq", int_x86_xop_vpshaq>;
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defm VPSHAD : xop3op<0x9A, "vpshad", int_x86_xop_vpshad>;
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defm VPSHAB : xop3op<0x98, "vpshab", int_x86_xop_vpshab>;
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defm VPROTW : xop3op<0x91, "vprotw", int_x86_xop_vprotw>;
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defm VPROTQ : xop3op<0x93, "vprotq", int_x86_xop_vprotq>;
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defm VPROTD : xop3op<0x92, "vprotd", int_x86_xop_vprotd>;
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defm VPROTB : xop3op<0x90, "vprotb", int_x86_xop_vprotb>;
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}
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multiclass xop3opimm<bits<8> opc, string OpcodeStr> {
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let neverHasSideEffects = 1 in {
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def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, i8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX;
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let mayLoad = 1 in
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def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins f128mem:$src1, i8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX;
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}
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}
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let isAsmParserOnly = 1 in {
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defm VPROTW : xop3opimm<0xC1, "vprotw">;
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defm VPROTQ : xop3opimm<0xC3, "vprotq">;
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defm VPROTD : xop3opimm<0xC2, "vprotd">;
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defm VPROTB : xop3opimm<0xC0, "vprotb">;
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}
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// Instruction where second source can be memory, but third must be register
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multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> {
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def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_4V, VEX_I8IMM;
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def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
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VR128:$src3))]>, VEX_4V, VEX_I8IMM;
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}
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let isAsmParserOnly = 1 in {
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defm VPMADCSWD : xop4opm2<0xB6, "vpmadcswd", int_x86_xop_vpmadcswd>;
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defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", int_x86_xop_vpmadcsswd>;
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defm VPMACSWW : xop4opm2<0x95, "vpmacsww", int_x86_xop_vpmacsww>;
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defm VPMACSWD : xop4opm2<0x96, "vpmacswd", int_x86_xop_vpmacswd>;
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defm VPMACSSWW : xop4opm2<0x85, "vpmacssww", int_x86_xop_vpmacssww>;
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defm VPMACSSWD : xop4opm2<0x86, "vpmacsswd", int_x86_xop_vpmacsswd>;
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defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", int_x86_xop_vpmacssdql>;
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defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", int_x86_xop_vpmacssdqh>;
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defm VPMACSSDD : xop4opm2<0x8E, "vpmacssdd", int_x86_xop_vpmacssdd>;
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defm VPMACSDQL : xop4opm2<0x97, "vpmacsdql", int_x86_xop_vpmacsdql>;
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defm VPMACSDQH : xop4opm2<0x9F, "vpmacsdqh", int_x86_xop_vpmacsdqh>;
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defm VPMACSDD : xop4opm2<0x9E, "vpmacsdd", int_x86_xop_vpmacsdd>;
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}
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// Instruction where second source can be memory, third must be imm8
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multiclass xop4opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType VT> {
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def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(VT (OpNode VR128:$src1, VR128:$src2, imm:$src3)))]>, VEX_4V;
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def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(VT (OpNode VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
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imm:$src3)))]>, VEX_4V;
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}
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let isAsmParserOnly = 1 in {
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defm VPCOMB : xop4opimm<0xCC, "vpcomb", X86vpcom, v16i8>;
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defm VPCOMW : xop4opimm<0xCD, "vpcomw", X86vpcom, v8i16>;
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defm VPCOMD : xop4opimm<0xCE, "vpcomd", X86vpcom, v4i32>;
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defm VPCOMQ : xop4opimm<0xCF, "vpcomq", X86vpcom, v2i64>;
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defm VPCOMUB : xop4opimm<0xEC, "vpcomub", X86vpcomu, v16i8>;
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defm VPCOMUW : xop4opimm<0xED, "vpcomuw", X86vpcomu, v8i16>;
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defm VPCOMUD : xop4opimm<0xEE, "vpcomud", X86vpcomu, v4i32>;
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defm VPCOMUQ : xop4opimm<0xEF, "vpcomuq", X86vpcomu, v2i64>;
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}
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// Instruction where either second or third source can be memory
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multiclass xop4op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
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def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst, (Int VR128:$src1, VR128:$src2, VR128:$src3))]>,
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VEX_4V, VEX_I8IMM;
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def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, VR128:$src2,
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(bitconvert (memopv2i64 addr:$src3))))]>,
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VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
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def mr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
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VR128:$src3))]>,
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VEX_4V, VEX_I8IMM;
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}
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let isAsmParserOnly = 1 in {
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defm VPPERM : xop4op<0xA3, "vpperm", int_x86_xop_vpperm>;
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defm VPCMOV : xop4op<0xA2, "vpcmov", int_x86_xop_vpcmov>;
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}
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multiclass xop4op256<bits<8> opc, string OpcodeStr, Intrinsic Int> {
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def rrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR256:$dst, (Int VR256:$src1, VR256:$src2, VR256:$src3))]>,
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VEX_4V, VEX_I8IMM;
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def rmY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR256:$dst,
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(Int VR256:$src1, VR256:$src2,
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(bitconvert (memopv4i64 addr:$src3))))]>,
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VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
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def mrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, f256mem:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR256:$dst,
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(Int VR256:$src1, (bitconvert (memopv4i64 addr:$src2)),
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VR256:$src3))]>,
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VEX_4V, VEX_I8IMM;
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}
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let isAsmParserOnly = 1 in {
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defm VPCMOV : xop4op256<0xA2, "vpcmov", int_x86_xop_vpcmov_256>;
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}
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multiclass xop5op<bits<8> opc, string OpcodeStr, Intrinsic Int128,
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Intrinsic Int256, PatFrag ld_128, PatFrag ld_256> {
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def rr : IXOP5<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3, i8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[(set VR128:$dst,
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(Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>;
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def rm : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[(set VR128:$dst,
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(Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>,
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VEX_W, MemOp4;
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def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[(set VR128:$dst,
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(Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
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def rrY : IXOP5<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3, i8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[(set VR256:$dst,
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(Int256 VR256:$src1, VR256:$src2, VR256:$src3, imm:$src4))]>;
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def rmY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
|
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[(set VR256:$dst,
|
|
(Int256 VR256:$src1, VR256:$src2, (ld_256 addr:$src3), imm:$src4))]>,
|
|
VEX_W, MemOp4;
|
|
def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
|
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(ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
|
|
[(set VR256:$dst,
|
|
(Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>;
|
|
}
|
|
|
|
defm VPERMIL2PD : xop5op<0x49, "vpermil2pd", int_x86_xop_vpermil2pd,
|
|
int_x86_xop_vpermil2pd_256, memopv2f64, memopv4f64>;
|
|
defm VPERMIL2PS : xop5op<0x48, "vpermil2ps", int_x86_xop_vpermil2ps,
|
|
int_x86_xop_vpermil2ps_256, memopv4f32, memopv8f32>;
|
|
|