mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-13 23:29:27 +00:00
14ccc9007a
This is for the lldb team so most of but not all of the values are to be printed as hex with this option. Some small values like the scale in an X86 address were requested to printed in decimal without the leading 0x. There may be some tweaks need to places that may still be in decimal that they want in hex. Specially for arm. I made my best guess. Any tweaks from here should be simple. I also did the best I know now with help from the C++ gurus creating the cleanest formatImm() utility function and containing the changes. But if someone has a better idea to make something cleaner I'm all ears and game for changing the implementation. rdar://8109283 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169393 91177308-0d34-0410-b5e6-96231b3b80d8
1451 lines
46 KiB
C++
1451 lines
46 KiB
C++
//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an ARM MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "ARMInstPrinter.h"
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#include "ARMGenAsmWriter.inc"
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/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
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///
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/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
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static unsigned translateShiftImm(unsigned imm) {
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// lsr #32 and asr #32 exist, but should be encoded as a 0.
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assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
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if (imm == 0)
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return 32;
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return imm;
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}
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/// Prints the shift value with an immediate value.
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static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
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unsigned ShImm, bool UseMarkup) {
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if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
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return;
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O << ", ";
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assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
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O << getShiftOpcStr(ShOpc);
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if (ShOpc != ARM_AM::rrx) {
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O << " ";
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if (UseMarkup)
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O << "<imm:";
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O << "#" << translateShiftImm(ShImm);
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if (UseMarkup)
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O << ">";
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}
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}
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ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI) :
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MCInstPrinter(MAI, MII, MRI) {
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// Initialize the set of available features.
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setAvailableFeatures(STI.getFeatureBits());
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}
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void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << markup("<reg:")
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<< getRegisterName(RegNo)
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<< markup(">");
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}
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void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot) {
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unsigned Opcode = MI->getOpcode();
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// Check for HINT instructions w/ canonical names.
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if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
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switch (MI->getOperand(0).getImm()) {
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case 0: O << "\tnop"; break;
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case 1: O << "\tyield"; break;
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case 2: O << "\twfe"; break;
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case 3: O << "\twfi"; break;
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case 4: O << "\tsev"; break;
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default:
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// Anything else should just print normally.
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printInstruction(MI, O);
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printAnnotation(O, Annot);
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return;
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}
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printPredicateOperand(MI, 1, O);
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if (Opcode == ARM::t2HINT)
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O << ".w";
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printAnnotation(O, Annot);
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return;
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}
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// Check for MOVs and print canonical forms, instead.
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if (Opcode == ARM::MOVsr) {
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// FIXME: Thumb variants?
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const MCOperand &Dst = MI->getOperand(0);
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const MCOperand &MO1 = MI->getOperand(1);
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const MCOperand &MO2 = MI->getOperand(2);
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const MCOperand &MO3 = MI->getOperand(3);
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O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
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printSBitModifierOperand(MI, 6, O);
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printPredicateOperand(MI, 4, O);
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O << '\t';
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printRegName(O, Dst.getReg());
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O << ", ";
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printRegName(O, MO1.getReg());
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O << ", ";
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printRegName(O, MO2.getReg());
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assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
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printAnnotation(O, Annot);
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return;
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}
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if (Opcode == ARM::MOVsi) {
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// FIXME: Thumb variants?
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const MCOperand &Dst = MI->getOperand(0);
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const MCOperand &MO1 = MI->getOperand(1);
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const MCOperand &MO2 = MI->getOperand(2);
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O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
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printSBitModifierOperand(MI, 5, O);
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printPredicateOperand(MI, 3, O);
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O << '\t';
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printRegName(O, Dst.getReg());
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O << ", ";
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printRegName(O, MO1.getReg());
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if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
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printAnnotation(O, Annot);
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return;
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}
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O << ", "
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<< markup("<imm:")
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<< "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()))
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<< markup(">");
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printAnnotation(O, Annot);
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return;
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}
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// A8.6.123 PUSH
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if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP &&
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MI->getNumOperands() > 5) {
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// Should only print PUSH if there are at least two registers in the list.
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O << '\t' << "push";
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printPredicateOperand(MI, 2, O);
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if (Opcode == ARM::t2STMDB_UPD)
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O << ".w";
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O << '\t';
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printRegisterList(MI, 4, O);
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printAnnotation(O, Annot);
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return;
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}
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if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
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MI->getOperand(3).getImm() == -4) {
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O << '\t' << "push";
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printPredicateOperand(MI, 4, O);
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O << "\t{";
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printRegName(O, MI->getOperand(1).getReg());
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O << "}";
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printAnnotation(O, Annot);
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return;
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}
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// A8.6.122 POP
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if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP &&
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MI->getNumOperands() > 5) {
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// Should only print POP if there are at least two registers in the list.
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O << '\t' << "pop";
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printPredicateOperand(MI, 2, O);
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if (Opcode == ARM::t2LDMIA_UPD)
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O << ".w";
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O << '\t';
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printRegisterList(MI, 4, O);
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printAnnotation(O, Annot);
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return;
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}
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if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
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MI->getOperand(4).getImm() == 4) {
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O << '\t' << "pop";
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printPredicateOperand(MI, 5, O);
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O << "\t{";
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printRegName(O, MI->getOperand(0).getReg());
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O << "}";
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printAnnotation(O, Annot);
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return;
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}
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// A8.6.355 VPUSH
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if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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O << '\t' << "vpush";
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printPredicateOperand(MI, 2, O);
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O << '\t';
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printRegisterList(MI, 4, O);
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printAnnotation(O, Annot);
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return;
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}
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// A8.6.354 VPOP
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if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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O << '\t' << "vpop";
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printPredicateOperand(MI, 2, O);
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O << '\t';
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printRegisterList(MI, 4, O);
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printAnnotation(O, Annot);
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return;
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}
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if (Opcode == ARM::tLDMIA) {
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bool Writeback = true;
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unsigned BaseReg = MI->getOperand(0).getReg();
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for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
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if (MI->getOperand(i).getReg() == BaseReg)
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Writeback = false;
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}
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O << "\tldm";
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printPredicateOperand(MI, 1, O);
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O << '\t';
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printRegName(O, BaseReg);
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if (Writeback) O << "!";
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O << ", ";
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printRegisterList(MI, 3, O);
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printAnnotation(O, Annot);
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return;
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}
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// Thumb1 NOP
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if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
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MI->getOperand(1).getReg() == ARM::R8) {
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O << "\tnop";
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printPredicateOperand(MI, 2, O);
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printAnnotation(O, Annot);
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return;
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}
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// Combine 2 GPRs from disassember into a GPRPair to match with instr def.
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// ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
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// a single GPRPair reg operand is used in the .td file to replace the two
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// GPRs. However, when decoding them, the two GRPs cannot be automatically
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// expressed as a GPRPair, so we have to manually merge them.
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// FIXME: We would really like to be able to tablegen'erate this.
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if (Opcode == ARM::LDREXD || Opcode == ARM::STREXD) {
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const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
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bool isStore = Opcode == ARM::STREXD;
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unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
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if (MRC.contains(Reg)) {
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MCInst NewMI;
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MCOperand NewReg;
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NewMI.setOpcode(Opcode);
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if (isStore)
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NewMI.addOperand(MI->getOperand(0));
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NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
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&MRI.getRegClass(ARM::GPRPairRegClassID)));
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NewMI.addOperand(NewReg);
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// Copy the rest operands into NewMI.
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for(unsigned i= isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
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NewMI.addOperand(MI->getOperand(i));
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printInstruction(&NewMI, O);
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return;
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}
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}
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printInstruction(MI, O);
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printAnnotation(O, Annot);
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}
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void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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unsigned Reg = Op.getReg();
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printRegName(O, Reg);
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} else if (Op.isImm()) {
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O << markup("<imm:")
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<< '#' << formatImm(Op.getImm())
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<< markup(">");
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} else {
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assert(Op.isExpr() && "unknown operand kind in printOperand");
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// If a symbolic branch target was added as a constant expression then print
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// that address in hex. And only print 32 unsigned bits for the address.
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const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
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int64_t Address;
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if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
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O << "0x";
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O.write_hex((uint32_t)Address);
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}
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else {
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// Otherwise, just print the expression.
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O << *Op.getExpr();
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}
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}
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}
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void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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if (MO1.isExpr())
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O << *MO1.getExpr();
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else if (MO1.isImm()) {
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O << markup("<mem:") << "[pc, "
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<< markup("<imm:") << "#" << formatImm(MO1.getImm())
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<< markup(">]>", "]");
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}
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else
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llvm_unreachable("Unknown LDR label operand?");
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}
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// so_reg is a 4-operand unit corresponding to register forms of the A5.1
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// "Addressing Mode 1 - Data-processing operands" forms. This includes:
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// REG 0 0 - e.g. R5
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// REG REG 0,SH_OPC - e.g. R5, ROR R3
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// REG 0 IMM,SH_OPC - e.g. R5, LSL #3
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void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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const MCOperand &MO3 = MI->getOperand(OpNum+2);
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printRegName(O, MO1.getReg());
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// Print the shift opc.
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ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
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O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
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if (ShOpc == ARM_AM::rrx)
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return;
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O << ' ';
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printRegName(O, MO2.getReg());
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assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
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}
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void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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printRegName(O, MO1.getReg());
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// Print the shift opc.
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printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
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ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #2
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//===--------------------------------------------------------------------===//
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void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(Op);
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const MCOperand &MO2 = MI->getOperand(Op+1);
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const MCOperand &MO3 = MI->getOperand(Op+2);
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O << markup("<mem:") << "[";
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printRegName(O, MO1.getReg());
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if (!MO2.getReg()) {
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if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
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O << ", "
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<< markup("<imm:")
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<< "#"
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
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<< ARM_AM::getAM2Offset(MO3.getImm())
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<< markup(">");
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}
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O << "]" << markup(">");
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return;
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}
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O << ", ";
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O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
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printRegName(O, MO2.getReg());
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printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
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ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
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O << "]" << markup(">");
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}
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void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(Op);
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const MCOperand &MO2 = MI->getOperand(Op+1);
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O << markup("<mem:") << "[";
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printRegName(O, MO1.getReg());
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O << ", ";
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printRegName(O, MO2.getReg());
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O << "]" << markup(">");
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}
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void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(Op);
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const MCOperand &MO2 = MI->getOperand(Op+1);
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O << markup("<mem:") << "[";
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printRegName(O, MO1.getReg());
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O << ", ";
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printRegName(O, MO2.getReg());
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O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
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}
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void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(Op);
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if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
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printOperand(MI, Op, O);
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return;
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}
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#ifndef NDEBUG
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const MCOperand &MO3 = MI->getOperand(Op+2);
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unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
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assert(IdxMode != ARMII::IndexModePost &&
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"Should be pre or offset index op");
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#endif
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printAM2PreOrOffsetIndexOp(MI, Op, O);
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}
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void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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if (!MO1.getReg()) {
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unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
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O << markup("<imm:")
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<< '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
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<< ImmOffs
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<< markup(">");
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return;
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}
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O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
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printRegName(O, MO1.getReg());
|
|
|
|
printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
|
|
ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Addressing Mode #3
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(Op);
|
|
const MCOperand &MO2 = MI->getOperand(Op+1);
|
|
const MCOperand &MO3 = MI->getOperand(Op+2);
|
|
|
|
O << markup("<mem:") << "[";
|
|
printRegName(O, MO1.getReg());
|
|
O << "], " << markup(">");
|
|
|
|
if (MO2.getReg()) {
|
|
O << (char)ARM_AM::getAM3Op(MO3.getImm());
|
|
printRegName(O, MO2.getReg());
|
|
return;
|
|
}
|
|
|
|
unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
|
|
O << markup("<imm:")
|
|
<< '#'
|
|
<< ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
|
|
<< ImmOffs
|
|
<< markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(Op);
|
|
const MCOperand &MO2 = MI->getOperand(Op+1);
|
|
const MCOperand &MO3 = MI->getOperand(Op+2);
|
|
|
|
O << markup("<mem:") << '[';
|
|
printRegName(O, MO1.getReg());
|
|
|
|
if (MO2.getReg()) {
|
|
O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
|
|
printRegName(O, MO2.getReg());
|
|
O << ']' << markup(">");
|
|
return;
|
|
}
|
|
|
|
//If the op is sub we have to print the immediate even if it is 0
|
|
unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
|
|
ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
|
|
|
|
if (ImmOffs || (op == ARM_AM::sub)) {
|
|
O << ", "
|
|
<< markup("<imm:")
|
|
<< "#"
|
|
<< ARM_AM::getAddrOpcStr(op)
|
|
<< ImmOffs
|
|
<< markup(">");
|
|
}
|
|
O << ']' << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(Op);
|
|
if (!MO1.isReg()) { // For label symbolic references.
|
|
printOperand(MI, Op, O);
|
|
return;
|
|
}
|
|
|
|
const MCOperand &MO3 = MI->getOperand(Op+2);
|
|
unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
|
|
|
|
if (IdxMode == ARMII::IndexModePost) {
|
|
printAM3PostIndexOp(MI, Op, O);
|
|
return;
|
|
}
|
|
printAM3PreOrOffsetIndexOp(MI, Op, O);
|
|
}
|
|
|
|
void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
if (MO1.getReg()) {
|
|
O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
|
|
printRegName(O, MO1.getReg());
|
|
return;
|
|
}
|
|
|
|
unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
|
|
O << markup("<imm:")
|
|
<< '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
|
|
<< markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO = MI->getOperand(OpNum);
|
|
unsigned Imm = MO.getImm();
|
|
O << markup("<imm:")
|
|
<< '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
|
|
<< markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << (MO2.getImm() ? "" : "-");
|
|
printRegName(O, MO1.getReg());
|
|
}
|
|
|
|
void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO = MI->getOperand(OpNum);
|
|
unsigned Imm = MO.getImm();
|
|
O << markup("<imm:")
|
|
<< '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
|
|
<< markup(">");
|
|
}
|
|
|
|
|
|
void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
|
|
.getImm());
|
|
O << ARM_AM::getAMSubModeStr(Mode);
|
|
}
|
|
|
|
void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
|
printOperand(MI, OpNum, O);
|
|
return;
|
|
}
|
|
|
|
O << markup("<mem:") << "[";
|
|
printRegName(O, MO1.getReg());
|
|
|
|
unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
|
|
unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
|
|
if (ImmOffs || Op == ARM_AM::sub) {
|
|
O << ", "
|
|
<< markup("<imm:")
|
|
<< "#"
|
|
<< ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
|
|
<< ImmOffs * 4
|
|
<< markup(">");
|
|
}
|
|
O << "]" << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << markup("<mem:") << "[";
|
|
printRegName(O, MO1.getReg());
|
|
if (MO2.getImm()) {
|
|
// FIXME: Both darwin as and GNU as violate ARM docs here.
|
|
O << ", :" << (MO2.getImm() << 3);
|
|
}
|
|
O << "]" << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
O << markup("<mem:") << "[";
|
|
printRegName(O, MO1.getReg());
|
|
O << "]" << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO = MI->getOperand(OpNum);
|
|
if (MO.getReg() == 0)
|
|
O << "!";
|
|
else {
|
|
O << ", ";
|
|
printRegName(O, MO.getReg());
|
|
}
|
|
}
|
|
|
|
void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO = MI->getOperand(OpNum);
|
|
uint32_t v = ~MO.getImm();
|
|
int32_t lsb = CountTrailingZeros_32(v);
|
|
int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
|
|
assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
|
|
O << markup("<imm:") << '#' << lsb << markup(">")
|
|
<< ", "
|
|
<< markup("<imm:") << '#' << width << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned val = MI->getOperand(OpNum).getImm();
|
|
O << ARM_MB::MemBOptToString(val);
|
|
}
|
|
|
|
void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned ShiftOp = MI->getOperand(OpNum).getImm();
|
|
bool isASR = (ShiftOp & (1 << 5)) != 0;
|
|
unsigned Amt = ShiftOp & 0x1f;
|
|
if (isASR) {
|
|
O << ", asr "
|
|
<< markup("<imm:")
|
|
<< "#" << (Amt == 0 ? 32 : Amt)
|
|
<< markup(">");
|
|
}
|
|
else if (Amt) {
|
|
O << ", lsl "
|
|
<< markup("<imm:")
|
|
<< "#" << Amt
|
|
<< markup(">");
|
|
}
|
|
}
|
|
|
|
void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Imm = MI->getOperand(OpNum).getImm();
|
|
if (Imm == 0)
|
|
return;
|
|
assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
|
|
O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Imm = MI->getOperand(OpNum).getImm();
|
|
// A shift amount of 32 is encoded as 0.
|
|
if (Imm == 0)
|
|
Imm = 32;
|
|
assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
|
|
O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "{";
|
|
for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
|
|
if (i != OpNum) O << ", ";
|
|
printRegName(O, MI->getOperand(i).getReg());
|
|
}
|
|
O << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Reg = MI->getOperand(OpNum).getReg();
|
|
printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
|
|
O << ", ";
|
|
printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
|
|
}
|
|
|
|
|
|
void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &Op = MI->getOperand(OpNum);
|
|
if (Op.getImm())
|
|
O << "be";
|
|
else
|
|
O << "le";
|
|
}
|
|
|
|
void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &Op = MI->getOperand(OpNum);
|
|
O << ARM_PROC::IModToString(Op.getImm());
|
|
}
|
|
|
|
void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &Op = MI->getOperand(OpNum);
|
|
unsigned IFlags = Op.getImm();
|
|
for (int i=2; i >= 0; --i)
|
|
if (IFlags & (1 << i))
|
|
O << ARM_PROC::IFlagsToString(1 << i);
|
|
|
|
if (IFlags == 0)
|
|
O << "none";
|
|
}
|
|
|
|
void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &Op = MI->getOperand(OpNum);
|
|
unsigned SpecRegRBit = Op.getImm() >> 4;
|
|
unsigned Mask = Op.getImm() & 0xf;
|
|
|
|
if (getAvailableFeatures() & ARM::FeatureMClass) {
|
|
unsigned SYSm = Op.getImm();
|
|
unsigned Opcode = MI->getOpcode();
|
|
// For reads of the special registers ignore the "mask encoding" bits
|
|
// which are only for writes.
|
|
if (Opcode == ARM::t2MRS_M)
|
|
SYSm &= 0xff;
|
|
switch (SYSm) {
|
|
default: llvm_unreachable("Unexpected mask value!");
|
|
case 0:
|
|
case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr
|
|
case 0x400: O << "apsr_g"; return;
|
|
case 0xc00: O << "apsr_nzcvqg"; return;
|
|
case 1:
|
|
case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr
|
|
case 0x401: O << "iapsr_g"; return;
|
|
case 0xc01: O << "iapsr_nzcvqg"; return;
|
|
case 2:
|
|
case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr
|
|
case 0x402: O << "eapsr_g"; return;
|
|
case 0xc02: O << "eapsr_nzcvqg"; return;
|
|
case 3:
|
|
case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
|
|
case 0x403: O << "xpsr_g"; return;
|
|
case 0xc03: O << "xpsr_nzcvqg"; return;
|
|
case 5:
|
|
case 0x805: O << "ipsr"; return;
|
|
case 6:
|
|
case 0x806: O << "epsr"; return;
|
|
case 7:
|
|
case 0x807: O << "iepsr"; return;
|
|
case 8:
|
|
case 0x808: O << "msp"; return;
|
|
case 9:
|
|
case 0x809: O << "psp"; return;
|
|
case 0x10:
|
|
case 0x810: O << "primask"; return;
|
|
case 0x11:
|
|
case 0x811: O << "basepri"; return;
|
|
case 0x12:
|
|
case 0x812: O << "basepri_max"; return;
|
|
case 0x13:
|
|
case 0x813: O << "faultmask"; return;
|
|
case 0x14:
|
|
case 0x814: O << "control"; return;
|
|
}
|
|
}
|
|
|
|
// As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
|
|
// APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
|
|
if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
|
|
O << "APSR_";
|
|
switch (Mask) {
|
|
default: llvm_unreachable("Unexpected mask value!");
|
|
case 4: O << "g"; return;
|
|
case 8: O << "nzcvq"; return;
|
|
case 12: O << "nzcvqg"; return;
|
|
}
|
|
}
|
|
|
|
if (SpecRegRBit)
|
|
O << "SPSR";
|
|
else
|
|
O << "CPSR";
|
|
|
|
if (Mask) {
|
|
O << '_';
|
|
if (Mask & 8) O << 'f';
|
|
if (Mask & 4) O << 's';
|
|
if (Mask & 2) O << 'x';
|
|
if (Mask & 1) O << 'c';
|
|
}
|
|
}
|
|
|
|
void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
|
|
// Handle the undefined 15 CC value here for printing so we don't abort().
|
|
if ((unsigned)CC == 15)
|
|
O << "<und>";
|
|
else if (CC != ARMCC::AL)
|
|
O << ARMCondCodeToString(CC);
|
|
}
|
|
|
|
void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
|
|
O << ARMCondCodeToString(CC);
|
|
}
|
|
|
|
void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
if (MI->getOperand(OpNum).getReg()) {
|
|
assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
|
|
"Expect ARM CPSR register!");
|
|
O << 's';
|
|
}
|
|
}
|
|
|
|
void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << MI->getOperand(OpNum).getImm();
|
|
}
|
|
|
|
void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "p" << MI->getOperand(OpNum).getImm();
|
|
}
|
|
|
|
void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "c" << MI->getOperand(OpNum).getImm();
|
|
}
|
|
|
|
void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "{" << MI->getOperand(OpNum).getImm() << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
|
|
}
|
|
|
|
void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO = MI->getOperand(OpNum);
|
|
|
|
if (MO.isExpr()) {
|
|
O << *MO.getExpr();
|
|
return;
|
|
}
|
|
|
|
int32_t OffImm = (int32_t)MO.getImm();
|
|
|
|
O << markup("<imm:");
|
|
if (OffImm == INT32_MIN)
|
|
O << "#-0";
|
|
else if (OffImm < 0)
|
|
O << "#-" << -OffImm;
|
|
else
|
|
O << "#" << OffImm;
|
|
O << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << markup("<imm:")
|
|
<< "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
|
|
<< markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Imm = MI->getOperand(OpNum).getImm();
|
|
O << markup("<imm:")
|
|
<< "#" << formatImm((Imm == 0 ? 32 : Imm))
|
|
<< markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// (3 - the number of trailing zeros) is the number of then / else.
|
|
unsigned Mask = MI->getOperand(OpNum).getImm();
|
|
unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
|
|
unsigned CondBit0 = Firstcond & 1;
|
|
unsigned NumTZ = CountTrailingZeros_32(Mask);
|
|
assert(NumTZ <= 3 && "Invalid IT mask!");
|
|
for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
|
|
bool T = ((Mask >> Pos) & 1) == CondBit0;
|
|
if (T)
|
|
O << 't';
|
|
else
|
|
O << 'e';
|
|
}
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(Op);
|
|
const MCOperand &MO2 = MI->getOperand(Op + 1);
|
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
|
printOperand(MI, Op, O);
|
|
return;
|
|
}
|
|
|
|
O << markup("<mem:") << "[";
|
|
printRegName(O, MO1.getReg());
|
|
if (unsigned RegNum = MO2.getReg()) {
|
|
O << ", ";
|
|
printRegName(O, RegNum);
|
|
}
|
|
O << "]" << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
|
|
unsigned Op,
|
|
raw_ostream &O,
|
|
unsigned Scale) {
|
|
const MCOperand &MO1 = MI->getOperand(Op);
|
|
const MCOperand &MO2 = MI->getOperand(Op + 1);
|
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
|
printOperand(MI, Op, O);
|
|
return;
|
|
}
|
|
|
|
O << markup("<mem:") << "[";
|
|
printRegName(O, MO1.getReg());
|
|
if (unsigned ImmOffs = MO2.getImm()) {
|
|
O << ", "
|
|
<< markup("<imm:")
|
|
<< "#" << formatImm(ImmOffs * Scale)
|
|
<< markup(">");
|
|
}
|
|
O << "]" << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
|
|
unsigned Op,
|
|
raw_ostream &O) {
|
|
printThumbAddrModeImm5SOperand(MI, Op, O, 1);
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
|
|
unsigned Op,
|
|
raw_ostream &O) {
|
|
printThumbAddrModeImm5SOperand(MI, Op, O, 2);
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
|
|
unsigned Op,
|
|
raw_ostream &O) {
|
|
printThumbAddrModeImm5SOperand(MI, Op, O, 4);
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
printThumbAddrModeImm5SOperand(MI, Op, O, 4);
|
|
}
|
|
|
|
// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
|
|
// register with shift forms.
|
|
// REG 0 0 - e.g. R5
|
|
// REG IMM, SH_OPC - e.g. R5, LSL #3
|
|
void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
unsigned Reg = MO1.getReg();
|
|
printRegName(O, Reg);
|
|
|
|
// Print the shift opc.
|
|
assert(MO2.isImm() && "Not a valid t2_so_reg value!");
|
|
printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
|
|
ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
|
|
}
|
|
|
|
void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
|
printOperand(MI, OpNum, O);
|
|
return;
|
|
}
|
|
|
|
O << markup("<mem:") << "[";
|
|
printRegName(O, MO1.getReg());
|
|
|
|
int32_t OffImm = (int32_t)MO2.getImm();
|
|
bool isSub = OffImm < 0;
|
|
// Special value for #-0. All others are normal.
|
|
if (OffImm == INT32_MIN)
|
|
OffImm = 0;
|
|
if (isSub) {
|
|
O << ", "
|
|
<< markup("<imm:")
|
|
<< "#-" << -OffImm
|
|
<< markup(">");
|
|
}
|
|
else if (OffImm > 0) {
|
|
O << ", "
|
|
<< markup("<imm:")
|
|
<< "#" << OffImm
|
|
<< markup(">");
|
|
}
|
|
O << "]" << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << markup("<mem:") << "[";
|
|
printRegName(O, MO1.getReg());
|
|
|
|
int32_t OffImm = (int32_t)MO2.getImm();
|
|
// Don't print +0.
|
|
if (OffImm != 0)
|
|
O << ", ";
|
|
if (OffImm != 0 && UseMarkup)
|
|
O << "<imm:";
|
|
if (OffImm == INT32_MIN)
|
|
O << "#-0";
|
|
else if (OffImm < 0)
|
|
O << "#-" << -OffImm;
|
|
else if (OffImm > 0)
|
|
O << "#" << OffImm;
|
|
if (OffImm != 0 && UseMarkup)
|
|
O << ">";
|
|
O << "]" << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
if (!MO1.isReg()) { // For label symbolic references.
|
|
printOperand(MI, OpNum, O);
|
|
return;
|
|
}
|
|
|
|
O << markup("<mem:") << "[";
|
|
printRegName(O, MO1.getReg());
|
|
|
|
int32_t OffImm = (int32_t)MO2.getImm();
|
|
|
|
assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
|
|
|
|
// Don't print +0.
|
|
if (OffImm != 0)
|
|
O << ", ";
|
|
if (OffImm != 0 && UseMarkup)
|
|
O << "<imm:";
|
|
if (OffImm == INT32_MIN)
|
|
O << "#-0";
|
|
else if (OffImm < 0)
|
|
O << "#-" << -OffImm;
|
|
else if (OffImm > 0)
|
|
O << "#" << OffImm;
|
|
if (OffImm != 0 && UseMarkup)
|
|
O << ">";
|
|
O << "]" << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << markup("<mem:") << "[";
|
|
printRegName(O, MO1.getReg());
|
|
if (MO2.getImm()) {
|
|
O << ", "
|
|
<< markup("<imm:")
|
|
<< "#" << formatImm(MO2.getImm() * 4)
|
|
<< markup(">");
|
|
}
|
|
O << "]" << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
int32_t OffImm = (int32_t)MO1.getImm();
|
|
O << ", " << markup("<imm:");
|
|
if (OffImm < 0)
|
|
O << "#-" << -OffImm;
|
|
else
|
|
O << "#" << OffImm;
|
|
O << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
int32_t OffImm = (int32_t)MO1.getImm();
|
|
|
|
assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
|
|
|
|
// Don't print +0.
|
|
if (OffImm != 0)
|
|
O << ", ";
|
|
if (OffImm != 0 && UseMarkup)
|
|
O << "<imm:";
|
|
if (OffImm == INT32_MIN)
|
|
O << "#-0";
|
|
else if (OffImm < 0)
|
|
O << "#-" << -OffImm;
|
|
else if (OffImm > 0)
|
|
O << "#" << OffImm;
|
|
if (OffImm != 0 && UseMarkup)
|
|
O << ">";
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
const MCOperand &MO3 = MI->getOperand(OpNum+2);
|
|
|
|
O << markup("<mem:") << "[";
|
|
printRegName(O, MO1.getReg());
|
|
|
|
assert(MO2.getReg() && "Invalid so_reg load / store address!");
|
|
O << ", ";
|
|
printRegName(O, MO2.getReg());
|
|
|
|
unsigned ShAmt = MO3.getImm();
|
|
if (ShAmt) {
|
|
assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
|
|
O << ", lsl "
|
|
<< markup("<imm:")
|
|
<< "#" << ShAmt
|
|
<< markup(">");
|
|
}
|
|
O << "]" << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO = MI->getOperand(OpNum);
|
|
O << markup("<imm:")
|
|
<< '#' << ARM_AM::getFPImmFloat(MO.getImm())
|
|
<< markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned EncodedImm = MI->getOperand(OpNum).getImm();
|
|
unsigned EltBits;
|
|
uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
|
|
O << markup("<imm:")
|
|
<< "#0x";
|
|
O.write_hex(Val);
|
|
O << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Imm = MI->getOperand(OpNum).getImm();
|
|
O << markup("<imm:")
|
|
<< "#" << formatImm(Imm + 1)
|
|
<< markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Imm = MI->getOperand(OpNum).getImm();
|
|
if (Imm == 0)
|
|
return;
|
|
O << ", ror "
|
|
<< markup("<imm:")
|
|
<< "#";
|
|
switch (Imm) {
|
|
default: assert (0 && "illegal ror immediate!");
|
|
case 1: O << "8"; break;
|
|
case 2: O << "16"; break;
|
|
case 3: O << "24"; break;
|
|
}
|
|
O << markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << markup("<imm:")
|
|
<< "#" << 16 - MI->getOperand(OpNum).getImm()
|
|
<< markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << markup("<imm:")
|
|
<< "#" << 32 - MI->getOperand(OpNum).getImm()
|
|
<< markup(">");
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "[" << MI->getOperand(OpNum).getImm() << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "{";
|
|
printRegName(O, MI->getOperand(OpNum).getReg());
|
|
O << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Reg = MI->getOperand(OpNum).getReg();
|
|
unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
|
|
unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
|
|
O << "{";
|
|
printRegName(O, Reg0);
|
|
O << ", ";
|
|
printRegName(O, Reg1);
|
|
O << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Reg = MI->getOperand(OpNum).getReg();
|
|
unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
|
|
unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
|
|
O << "{";
|
|
printRegName(O, Reg0);
|
|
O << ", ";
|
|
printRegName(O, Reg1);
|
|
O << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// Normally, it's not safe to use register enum values directly with
|
|
// addition to get the next register, but for VFP registers, the
|
|
// sort order is guaranteed because they're all of the form D<n>.
|
|
O << "{";
|
|
printRegName(O, MI->getOperand(OpNum).getReg());
|
|
O << ", ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 1);
|
|
O << ", ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 2);
|
|
O << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// Normally, it's not safe to use register enum values directly with
|
|
// addition to get the next register, but for VFP registers, the
|
|
// sort order is guaranteed because they're all of the form D<n>.
|
|
O << "{";
|
|
printRegName(O, MI->getOperand(OpNum).getReg());
|
|
O << ", ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 1);
|
|
O << ", ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 2);
|
|
O << ", ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 3);
|
|
O << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "{";
|
|
printRegName(O, MI->getOperand(OpNum).getReg());
|
|
O << "[]}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Reg = MI->getOperand(OpNum).getReg();
|
|
unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
|
|
unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
|
|
O << "{";
|
|
printRegName(O, Reg0);
|
|
O << "[], ";
|
|
printRegName(O, Reg1);
|
|
O << "[]}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// Normally, it's not safe to use register enum values directly with
|
|
// addition to get the next register, but for VFP registers, the
|
|
// sort order is guaranteed because they're all of the form D<n>.
|
|
O << "{";
|
|
printRegName(O, MI->getOperand(OpNum).getReg());
|
|
O << "[], ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 1);
|
|
O << "[], ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 2);
|
|
O << "[]}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// Normally, it's not safe to use register enum values directly with
|
|
// addition to get the next register, but for VFP registers, the
|
|
// sort order is guaranteed because they're all of the form D<n>.
|
|
O << "{";
|
|
printRegName(O, MI->getOperand(OpNum).getReg());
|
|
O << "[], ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 1);
|
|
O << "[], ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 2);
|
|
O << "[], ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 3);
|
|
O << "[]}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Reg = MI->getOperand(OpNum).getReg();
|
|
unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
|
|
unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
|
|
O << "{";
|
|
printRegName(O, Reg0);
|
|
O << "[], ";
|
|
printRegName(O, Reg1);
|
|
O << "[]}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// Normally, it's not safe to use register enum values directly with
|
|
// addition to get the next register, but for VFP registers, the
|
|
// sort order is guaranteed because they're all of the form D<n>.
|
|
O << "{";
|
|
printRegName(O, MI->getOperand(OpNum).getReg());
|
|
O << "[], ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 2);
|
|
O << "[], ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 4);
|
|
O << "[]}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// Normally, it's not safe to use register enum values directly with
|
|
// addition to get the next register, but for VFP registers, the
|
|
// sort order is guaranteed because they're all of the form D<n>.
|
|
O << "{";
|
|
printRegName(O, MI->getOperand(OpNum).getReg());
|
|
O << "[], ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 2);
|
|
O << "[], ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 4);
|
|
O << "[], ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 6);
|
|
O << "[]}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// Normally, it's not safe to use register enum values directly with
|
|
// addition to get the next register, but for VFP registers, the
|
|
// sort order is guaranteed because they're all of the form D<n>.
|
|
O << "{";
|
|
printRegName(O, MI->getOperand(OpNum).getReg());
|
|
O << ", ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 2);
|
|
O << ", ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 4);
|
|
O << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// Normally, it's not safe to use register enum values directly with
|
|
// addition to get the next register, but for VFP registers, the
|
|
// sort order is guaranteed because they're all of the form D<n>.
|
|
O << "{";
|
|
printRegName(O, MI->getOperand(OpNum).getReg());
|
|
O << ", ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 2);
|
|
O << ", ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 4);
|
|
O << ", ";
|
|
printRegName(O, MI->getOperand(OpNum).getReg() + 6);
|
|
O << "}";
|
|
}
|