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https://github.com/c64scene-ar/llvm-6502.git
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6b7d99d473
This patch replaces the control flow handling with a new pass which structurize the graph before transforming it to machine instruction. This has a couple of different advantages and currently fixes 20 piglit tests without a single regression. It is now a general purpose transformation that could be not only be used for SI/R6xx, but also for other hardware implementations that use a form of structurized control flow. v2: further cleanup, fixes and documentation Patch by: Christian König Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170591 91177308-0d34-0410-b5e6-96231b3b80d8
53 lines
2.6 KiB
TableGen
53 lines
2.6 KiB
TableGen
//===-- SIIntrinsics.td - SI Intrinsic defs ----------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// SI Intrinsic Definitions
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//
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "SI", isTarget = 1 in {
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def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_SI_export : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], []>;
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/* XXX: We may need a seperate intrinsic here for loading integer values */
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def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_i64_ty, llvm_i32_ty], []>;
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def int_SI_vs_load_buffer_index : Intrinsic <[llvm_i32_ty], [], [IntrNoMem]>;
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def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_v4i32_ty, llvm_i16_ty, llvm_i32_ty], [IntrReadMem]> ;
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def int_SI_wqm : Intrinsic <[], [], []>;
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def int_SI_sample : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_v4f32_ty, llvm_v8i32_ty, llvm_v4i32_ty], [IntrReadMem]>;
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def int_SI_sample_bias : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_v4f32_ty, llvm_v8i32_ty, llvm_v4i32_ty], [IntrReadMem]>;
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def int_SI_sample_lod : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_v4f32_ty, llvm_v8i32_ty, llvm_v4i32_ty], [IntrReadMem]>;
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/* Interpolation Intrinsics */
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def int_SI_set_M0 : Intrinsic <[llvm_i32_ty], [llvm_i32_ty]>;
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class Interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadMem]>;
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def int_SI_fs_interp_linear_center : Interp;
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def int_SI_fs_interp_linear_centroid : Interp;
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def int_SI_fs_interp_persp_center : Interp;
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def int_SI_fs_interp_persp_centroid : Interp;
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def int_SI_fs_interp_constant : Interp;
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def int_SI_fs_read_face : Intrinsic <[llvm_float_ty], [], [IntrNoMem]>;
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def int_SI_fs_read_pos : Intrinsic <[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
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/* Control flow Intrinsics */
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def int_SI_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], []>;
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def int_SI_else : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_empty_ty], []>;
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def int_SI_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], []>;
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def int_SI_if_break : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_i64_ty], []>;
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def int_SI_else_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], []>;
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def int_SI_loop : Intrinsic<[], [llvm_i64_ty, llvm_empty_ty], []>;
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def int_SI_end_cf : Intrinsic<[], [llvm_i64_ty], []>;
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}
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