llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-02 22:32:38 +00:00

History

Dan Gohman f350b277f3 Move the point at which FastISel taps into the SelectionDAGISel process up to a higher level. This allows FastISel to leverage more of SelectionDAGISel's infastructure, such as updating Machine PHI nodes. Also, implement transitioning from SDISel back to FastISel in the middle of a block, so it's now possible to go back and forth. This allows FastISel to hand individual CallInsts and other complicated things off to SDISel to handle, while handling the rest of the block itself. To help support this, reorganize the SelectionDAG class so that it is allocated once and reused throughout a function, instead of being completely reallocated for each block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8		2008-08-23 02:25:05 +00:00
..
Alpha.h	Use raw_ostream throughout the AsmPrinter.	2008-08-21 00:14:44 +00:00
Alpha.td
AlphaAsmPrinter.cpp	Use raw_ostream throughout the AsmPrinter.	2008-08-21 00:14:44 +00:00
AlphaBranchSelector.cpp
AlphaCodeEmitter.cpp	Unbreak JIT. Ignore TargetInstrInfo::IMPLICIT_DEF.	2008-03-17 06:56:52 +00:00
AlphaInstrFormats.td	llvm.memory.barrier, and impl for x86 and alpha	2008-02-16 01:24:58 +00:00
AlphaInstrInfo.cpp	Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.	2008-08-14 22:49:33 +00:00
AlphaInstrInfo.h	Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.	2008-08-14 22:49:33 +00:00
AlphaInstrInfo.td	Tablegen generated code already tests the opcode value, so it's not	2008-08-20 15:24:22 +00:00
AlphaISelDAGToDAG.cpp	Move the point at which FastISel taps into the SelectionDAGISel	2008-08-23 02:25:05 +00:00
AlphaISelLowering.cpp	Rename SDOperand to SDValue.	2008-07-27 21:46:04 +00:00
AlphaISelLowering.h	Rename SDOperand to SDValue.	2008-07-27 21:46:04 +00:00
AlphaJITInfo.cpp	Correlate stubs with functions in JIT: when emitting a stub, the JIT tells the memory manager which function	2008-04-16 20:46:05 +00:00
AlphaJITInfo.h	Trim #includes.	2008-08-05 15:32:23 +00:00
AlphaLLRP.cpp	Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.	2008-03-15 00:03:38 +00:00
AlphaRegisterInfo.cpp	Pool-allocation for MachineInstrs, MachineBasicBlocks, and	2008-07-07 23:14:23 +00:00
AlphaRegisterInfo.h	Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.	2008-03-31 20:40:39 +00:00
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetAsmInfo.cpp
AlphaTargetAsmInfo.h
AlphaTargetMachine.cpp	Use raw_ostream throughout the AsmPrinter.	2008-08-21 00:14:44 +00:00
AlphaTargetMachine.h	Use raw_ostream throughout the AsmPrinter.	2008-08-21 00:14:44 +00:00
Makefile
README.txt

README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html