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d9accc1e5f
filler such as if delay slot filler have to put NOP instruction into the delay slot of microMIPS BEQ or BNE instruction which uses the register $0, then instead of emitting NOP this instruction is replaced by the corresponding microMIPS compact branch instruction, i.e. BEQZC or BNEZC. Differential Revision: http://reviews.llvm.org/D3566 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222580 91177308-0d34-0410-b5e6-96231b3b80d8
20 lines
415 B
LLVM
20 lines
415 B
LLVM
; RUN: llc %s -march=mipsel -mattr=micromips -filetype=asm -O3 \
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; RUN: -disable-mips-delay-filler -relocation-model=pic -o - | FileCheck %s
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define void @main() nounwind uwtable {
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entry:
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%x = alloca i32, align 4
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%0 = load i32* %x, align 4
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%cmp = icmp eq i32 %0, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 10, i32* %x, align 4
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br label %if.end
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if.end:
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ret void
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}
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; CHECK: bnezc
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