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1c3d19eb15
* Enhanced tblgen to handle instructions which have chain operand and writes a chain result. * Enhanced tblgen to handle instructions which produces no results. Part of the change is a temporary hack which relies on instruction property (e.g. isReturn, isBranch). The proper fix would be to change the .td syntax to separate results dag from ops dag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24587 91177308-0d34-0410-b5e6-96231b3b80d8
99 lines
3.4 KiB
C++
99 lines
3.4 KiB
C++
//===- CodeGenInstruction.h - Instruction Class Wrapper ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a wrapper class for the 'Instruction' TableGen class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CODEGEN_INSTRUCTION_H
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#define CODEGEN_INSTRUCTION_H
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#include "llvm/CodeGen/ValueTypes.h"
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#include <string>
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#include <vector>
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#include <utility>
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namespace llvm {
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class Record;
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class DagInit;
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struct CodeGenInstruction {
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Record *TheDef; // The actual record defining this instruction.
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std::string Name; // Contents of the 'Name' field.
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std::string Namespace; // The namespace the instruction is in.
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/// AsmString - The format string used to emit a .s file for the
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/// instruction.
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std::string AsmString;
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/// OperandInfo - The information we keep track of for each operand in the
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/// operand list for a tablegen instruction.
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struct OperandInfo {
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/// Rec - The definition this operand is declared as.
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///
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Record *Rec;
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/// Name - If this operand was assigned a symbolic name, this is it,
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/// otherwise, it's empty.
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std::string Name;
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/// PrinterMethodName - The method used to print operands of this type in
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/// the asmprinter.
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std::string PrinterMethodName;
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/// MIOperandNo - Currently (this is meant to be phased out), some logical
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/// operands correspond to multiple MachineInstr operands. In the X86
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/// target for example, one address operand is represented as 4
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/// MachineOperands. Because of this, the operand number in the
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/// OperandList may not match the MachineInstr operand num. Until it
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/// does, this contains the MI operand index of this operand.
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unsigned MIOperandNo;
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unsigned MINumOperands; // The number of operands.
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/// MIOperandInfo - Default MI operand type. Note an operand may be made
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/// up of multiple MI operands.
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DagInit *MIOperandInfo;
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OperandInfo(Record *R, const std::string &N, const std::string &PMN,
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unsigned MION, unsigned MINO, DagInit *MIOI)
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: Rec(R), Name(N), PrinterMethodName(PMN), MIOperandNo(MION),
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MINumOperands(MINO), MIOperandInfo(MIOI) {}
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};
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/// OperandList - The list of declared operands, along with their declared
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/// type (which is a record).
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std::vector<OperandInfo> OperandList;
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// Various boolean values we track for the instruction.
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bool isReturn;
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bool isBranch;
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bool isBarrier;
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bool isCall;
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bool isLoad;
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bool isStore;
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bool isTwoAddress;
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bool isConvertibleToThreeAddress;
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bool isCommutable;
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bool isTerminator;
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bool hasDelaySlot;
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bool usesCustomDAGSchedInserter;
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bool hasVariableNumberOfOperands;
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bool hasCtrlDep;
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CodeGenInstruction(Record *R, const std::string &AsmStr);
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/// getOperandNamed - Return the index of the operand with the specified
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/// non-empty name. If the instruction does not have an operand with the
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/// specified name, throw an exception.
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unsigned getOperandNamed(const std::string &Name) const;
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};
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}
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#endif
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